# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify that when a function has the speculative_load_hardening attribute we
# never produce a CB(N)Z or TB(N)Z.
#

--- |
    define void @no_tbnz() speculative_load_hardening { ret void }
    define void @no_cbz() speculative_load_hardening { ret void }
    define void @fp() speculative_load_hardening { ret void }
...

---
name:            no_tbnz
legalized:       true
regBankSelected: true
body:             |
  ; CHECK-LABEL: name: no_tbnz
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   %reg:gpr32 = COPY $w0
  ; CHECK:   [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg, 1, implicit-def $nzcv
  ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  ; CHECK:   RET_ReallyLR
  bb.0:
    liveins: $w0
    successors: %bb.0, %bb.1
    %reg:gpr(s32) = COPY $w0
    %cond:gpr(s1) = G_TRUNC %reg
    G_BRCOND %cond(s1), %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR
...
---
name:            no_cbz
legalized:       true
regBankSelected: true
body:             |
  ; CHECK-LABEL: name: no_cbz
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   %reg:gpr32sp = COPY $w0
  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg, 0, 0, implicit-def $nzcv
  ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  ; CHECK:   RET_ReallyLR
  bb.0:
    liveins: $w0
    successors: %bb.0, %bb.1
    %reg:gpr(s32) = COPY $w0
    %zero:gpr(s32) = G_CONSTANT i32 0
    %cmp:gpr(s32) = G_ICMP intpred(eq), %reg, %zero
    %cond:gpr(s1) = G_TRUNC %cmp(s32)
    G_BRCOND %cond(s1), %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR
...
---
name:            fp
legalized:       true
regBankSelected: true
body:             |
  ; CHECK-LABEL: name: fp
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.0(0x40000000), %bb.1(0x40000000)
  ; CHECK:   %reg0:fpr32 = COPY $s0
  ; CHECK:   %reg1:fpr32 = COPY $s1
  ; CHECK:   FCMPSrr %reg0, %reg1, implicit-def $nzcv
  ; CHECK:   Bcc 0, %bb.1, implicit $nzcv
  ; CHECK:   B %bb.0
  ; CHECK: bb.1:
  ; CHECK:   RET_ReallyLR
  bb.0:
    liveins: $s0, $s1
    successors: %bb.0, %bb.1
    %reg0:fpr(s32) = COPY $s0
    %reg1:fpr(s32) = COPY $s1
    %cmp:gpr(s32) = G_FCMP floatpred(oeq), %reg0, %reg1
    %cond:gpr(s1) = G_TRUNC %cmp(s32)
    G_BRCOND %cond(s1), %bb.1
    G_BR %bb.0
  bb.1:
    RET_ReallyLR