# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Verify that we can fold compares into integer selects.
#
# This is an integer version of fold-fp-select.mir.
#

...
---
name:            eq
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: eq
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
    ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY1]], 0, implicit $nzcv
    ; CHECK: $w0 = COPY [[CSELWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = COPY $w1
    %2:gpr(s32) = G_CONSTANT i32 0
    %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
    %3:gpr(s1) = G_TRUNC %5(s32)
    %4:gpr(s32) = G_SELECT %3(s1), %2, %1
    $w0 = COPY %4(s32)
    RET_ReallyLR implicit $w0

...
---
name:            using_fcmp
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $s0, $w0, $w1

    ; CHECK-LABEL: name: using_fcmp
    ; CHECK: liveins: $s0, $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
    ; CHECK: FCMPSri [[COPY1]], implicit-def $nzcv
    ; CHECK: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY2]], [[COPY]], 0, implicit $nzcv
    ; CHECK: $w0 = COPY [[CSELWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %1:gpr(s32) = COPY $w1
    %2:fpr(s32) = COPY $s0
    %3:fpr(s32) = G_FCONSTANT float 0.000000e+00
    %6:gpr(s32) = G_CONSTANT i32 0
    %7:gpr(s32) = G_FCMP floatpred(oeq), %2(s32), %3
    %4:gpr(s1) = G_TRUNC %7(s32)
    %5:gpr(s32) = G_SELECT %4(s1), %6, %1
    $w0 = COPY %5(s32)
    RET_ReallyLR implicit $w0

...
---
name:            csinc
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0, $w1

    ; CHECK-LABEL: name: csinc
    ; CHECK: liveins: $w0, $w1
    ; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY]], $wzr, 0, implicit $nzcv
    ; CHECK: $w0 = COPY [[CSINCWr]]
    ; CHECK: RET_ReallyLR implicit $w0
    %0:gpr(s32) = COPY $w0
    %1:gpr(s32) = COPY $w1
    %2:gpr(s32) = G_CONSTANT i32 1
    %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2
    %3:gpr(s1) = G_TRUNC %5(s32)
    %4:gpr(s32) = G_SELECT %3(s1), %0, %2
    $w0 = COPY %4(s32)
    RET_ReallyLR implicit $w0
...