AMD family 17h (znver1) enablement
Summary:
This patch enables the following
1. AMD family 17h architecture using "znver1" tune flag (-march, -mcpu).
2. ISAs that are enabled for "znver1" architecture.
3. Checks ADX isa from cpuid to identify "znver1" flag when -march=native is used.
4. ISAs FMA4, XOP are disabled as they are dropped from amdfam17.
5. For the time being, it uses the btver2 scheduler model.
6. Test file is updated to check this flag.
This is linked to llvm review item https://reviews.llvm.org/D28017
Patch by Ganesh Gopalasubramanian. Additional test cases added by Craig Topper.
Reviewers: RKSimon, craig.topper
Subscribers: cfe-commits, RKSimon, ashutosh.nema, llvm-commits
Differential Revision: https://reviews.llvm.org/D28018
llvm-svn: 291544
diff --git a/clang/test/Preprocessor/predefined-arch-macros.c b/clang/test/Preprocessor/predefined-arch-macros.c
index 51b587e..883cc4d 100644
--- a/clang/test/Preprocessor/predefined-arch-macros.c
+++ b/clang/test/Preprocessor/predefined-arch-macros.c
@@ -1849,6 +1849,88 @@
// CHECK_BDVER4_M64: #define __tune_bdver4__ 1
// CHECK_BDVER4_M64: #define __x86_64 1
// CHECK_BDVER4_M64: #define __x86_64__ 1
+// RUN: %clang -march=znver1 -m32 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M32
+// CHECK_ZNVER1_M32-NOT: #define __3dNOW_A__ 1
+// CHECK_ZNVER1_M32-NOT: #define __3dNOW__ 1
+// CHECK_ZNVER1_M32: #define __ADX__ 1
+// CHECK_ZNVER1_M32: #define __AES__ 1
+// CHECK_ZNVER1_M32: #define __AVX2__ 1
+// CHECK_ZNVER1_M32: #define __AVX__ 1
+// CHECK_ZNVER1_M32: #define __BMI2__ 1
+// CHECK_ZNVER1_M32: #define __BMI__ 1
+// CHECK_ZNVER1_M32: #define __F16C__ 1
+// CHECK_ZNVER1_M32: #define __FMA__ 1
+// CHECK_ZNVER1_M32: #define __FSGSBASE__ 1
+// CHECK_ZNVER1_M32: #define __LZCNT__ 1
+// CHECK_ZNVER1_M32: #define __MMX__ 1
+// CHECK_ZNVER1_M32: #define __PCLMUL__ 1
+// CHECK_ZNVER1_M32: #define __POPCNT__ 1
+// CHECK_ZNVER1_M32: #define __PRFCHW__ 1
+// CHECK_ZNVER1_M32: #define __RDRND__ 1
+// CHECK_ZNVER1_M32: #define __RDSEED__ 1
+// CHECK_ZNVER1_M32: #define __SHA__ 1
+// CHECK_ZNVER1_M32: #define __SSE2_MATH__ 1
+// CHECK_ZNVER1_M32: #define __SSE2__ 1
+// CHECK_ZNVER1_M32: #define __SSE3__ 1
+// CHECK_ZNVER1_M32: #define __SSE4A__ 1
+// CHECK_ZNVER1_M32: #define __SSE4_1__ 1
+// CHECK_ZNVER1_M32: #define __SSE4_2__ 1
+// CHECK_ZNVER1_M32: #define __SSE_MATH__ 1
+// CHECK_ZNVER1_M32: #define __SSE__ 1
+// CHECK_ZNVER1_M32: #define __SSSE3__ 1
+// CHECK_ZNVER1_M32: #define __XSAVEC__ 1
+// CHECK_ZNVER1_M32: #define __XSAVEOPT__ 1
+// CHECK_ZNVER1_M32: #define __XSAVES__ 1
+// CHECK_ZNVER1_M32: #define __XSAVE__ 1
+// CHECK_ZNVER1_M32: #define __i386 1
+// CHECK_ZNVER1_M32: #define __i386__ 1
+// CHECK_ZNVER1_M32: #define __tune_znver1__ 1
+// CHECK_ZNVER1_M32: #define __znver1 1
+// CHECK_ZNVER1_M32: #define __znver1__ 1
+// RUN: %clang -march=znver1 -m64 -E -dM %s -o - 2>&1 \
+// RUN: -target i386-unknown-linux \
+// RUN: | FileCheck -match-full-lines %s -check-prefix=CHECK_ZNVER1_M64
+// CHECK_ZNVER1_M64-NOT: #define __3dNOW_A__ 1
+// CHECK_ZNVER1_M64-NOT: #define __3dNOW__ 1
+// CHECK_ZNVER1_M64: #define __ADX__ 1
+// CHECK_ZNVER1_M64: #define __AES__ 1
+// CHECK_ZNVER1_M64: #define __AVX2__ 1
+// CHECK_ZNVER1_M64: #define __AVX__ 1
+// CHECK_ZNVER1_M64: #define __BMI2__ 1
+// CHECK_ZNVER1_M64: #define __BMI__ 1
+// CHECK_ZNVER1_M64: #define __F16C__ 1
+// CHECK_ZNVER1_M64: #define __FMA__ 1
+// CHECK_ZNVER1_M64: #define __FSGSBASE__ 1
+// CHECK_ZNVER1_M64: #define __LZCNT__ 1
+// CHECK_ZNVER1_M64: #define __MMX__ 1
+// CHECK_ZNVER1_M64: #define __PCLMUL__ 1
+// CHECK_ZNVER1_M64: #define __POPCNT__ 1
+// CHECK_ZNVER1_M64: #define __PRFCHW__ 1
+// CHECK_ZNVER1_M64: #define __RDRND__ 1
+// CHECK_ZNVER1_M64: #define __RDSEED__ 1
+// CHECK_ZNVER1_M64: #define __SHA__ 1
+// CHECK_ZNVER1_M64: #define __SSE2_MATH__ 1
+// CHECK_ZNVER1_M64: #define __SSE2__ 1
+// CHECK_ZNVER1_M64: #define __SSE3__ 1
+// CHECK_ZNVER1_M64: #define __SSE4A__ 1
+// CHECK_ZNVER1_M64: #define __SSE4_1__ 1
+// CHECK_ZNVER1_M64: #define __SSE4_2__ 1
+// CHECK_ZNVER1_M64: #define __SSE_MATH__ 1
+// CHECK_ZNVER1_M64: #define __SSE__ 1
+// CHECK_ZNVER1_M64: #define __SSSE3__ 1
+// CHECK_ZNVER1_M64: #define __XSAVEC__ 1
+// CHECK_ZNVER1_M64: #define __XSAVEOPT__ 1
+// CHECK_ZNVER1_M64: #define __XSAVES__ 1
+// CHECK_ZNVER1_M64: #define __XSAVE__ 1
+// CHECK_ZNVER1_M64: #define __amd64 1
+// CHECK_ZNVER1_M64: #define __amd64__ 1
+// CHECK_ZNVER1_M64: #define __tune_znver1__ 1
+// CHECK_ZNVER1_M64: #define __x86_64 1
+// CHECK_ZNVER1_M64: #define __x86_64__ 1
+// CHECK_ZNVER1_M64: #define __znver1 1
+// CHECK_ZNVER1_M64: #define __znver1__ 1
//
// End X86/GCC/Linux tests ------------------
