[AArch64] Split zero cycle zeoring per register class (#154561)

This change improves LLVM's model accuracy by splitting AArch64
subtarget features of zero cycle zeroing per register class. This aligns
with how uarch is designed (each register bank has unique capabilities).
Similarly to how we improved ZCM modeling.

It splits `HasZeroCycleZeroingGP` to `HasZeroCycleZeroingGPR32` and
`HasZeroCycleZeroingGPR64`, removes opaque `FeatureZCZeroing`, and
infers `FeatureNoZCZeroingFP` to be `FeatureNoZCZeroingFPR64` based on
the single usage in `AArch64AsmPrinter.cpp`.

It also splits `arm64-zero-cycle-zeroing.ll` into 2 tests one `-gpr` and
one `-fpr`, similarly to ZCM, to make the tests more focused and
managable in correspondance with the new modeling.

The test cases are updated as well, exlpoiting the fact that this is a
refactor patch:

- remove redundant functions that just mix isolated ones (t1-4)
- specialize check prefixes
- replace `apple-a10` with `apple-m1`
- add a `-mtriple=arm64-apple-macosx -mcpu=generic` test case for GPR
- isolate `mtriple=arm64-apple-ios -mcpu=cyclone` FP workaround test
case and move `-fullfp16` to another non-workaround test case