commit | c22bc215ac9496ee5f6e55ba0b0904dc825c6f56 | [log] [tgz] |
---|---|---|
author | Mallikarjuna Gouda <mgouda@mips.com> | Sun May 04 10:48:19 2025 +0530 |
committer | GitHub <noreply@github.com> | Sun May 04 01:18:19 2025 -0400 |
tree | ebd050702c288c0f1e8205d7ab14da457a8cf323 | |
parent | 2d287f51eff2a5fbf84458a33f7fb2493cf67965 [diff] |
[MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) (#137984) Relands #132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf
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