[CIR][AArch64] Add lowering for predicated SVE svdup builtins (zeroing) (#175976)

This PR adds CIR lowering support for predicated SVE `svdup` builtins on
AArch64. The corresponding ACLE intrinsics are documented at:
  https://developer.arm.com/architectures/instruction-sets/intrinsics

This change focuses on the zeroing-predicated variants (suffix `_z`,
e.g. `svdup_n_f32_z`), which lower to the LLVM SVE `dup` intrinsic
with a `zeroinitializer` passthrough operand.

IMPLEMENTATION NOTES
--------------------
* The CIR type converter is extended to support `BuiltinType::SveBool`,
  which is lowered to `cir.vector<[16] x i1>`, matching current Clang
  behaviour and ensuring compatibility with existing LLVM SVE lowering.
* Added logic that converts `cir.vector<[16] x i1>` according to the
  underlying element type. This is done by calling
  `@llvm.aarch64.sve.convert.from.svbool`.

TEST NOTES
----------
Compared to the unpredicated `svdup` tests
(https://github.com/llvm/llvm-project/pull/174433), the new tests
perform more explicit checks to verify:
  * Correct argument usage
  * Correct return value + type

This helped validate differences between the default Clang lowering and
the CIR-based lowering. Once all `svdup` variants are implemented, the tests
will be unified.

EXAMPLE LOWERING
----------------
The following example illustrates that CIR lowering produces equivalent
LLVM IR to the default Clang path.

Input:
```c
svint8_t test_svdup_n_s8(svbool_t pg, int8_t op) {
  return svdup_n_s8_z(pg, op);
}

OUTPUT 1 (default):
```llvm
define dso_local <vscale x 16 x i8> @test(<vscale x 16 x i1> %pg, i8
noundef %op) #0 {
entry:
  %pg.addr = alloca <vscale x 16 x i1>, align 2
  %op.addr = alloca i8, align 1
  store <vscale x 16 x i1> %pg, ptr %pg.addr, align 2
  store i8 %op, ptr %op.addr, align 1
  %0 = load <vscale x 16 x i1>, ptr %pg.addr, align 2
  %1 = load i8, ptr %op.addr, align 1
%2 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16
x i8> zeroinitializer, <vscale x 16 x i1> %0, i8 %1)
  ret <vscale x 16 x i8> %2
}
```

OUTPUT 2 (via `-fclangir`):
```llvm
; Function Attrs: noinline
define dso_local <vscale x 16 x i8> @test(<vscale x 16 x i1> %0, i8 %1)
#0 {
  %3 = alloca <vscale x 16 x i1>, i64 1, align 2
  %4 = alloca i8, i64 1, align 1
  %5 = alloca <vscale x 16 x i8>, i64 1, align 16
  store <vscale x 16 x i1> %0, ptr %3, align 2
  store i8 %1, ptr %4, align 1
  %6 = load <vscale x 16 x i1>, ptr %3, align 2
  %7 = load i8, ptr %4, align 1
%8 = call <vscale x 16 x i8> @llvm.aarch64.sve.dup.nxv16i8(<vscale x 16
x i8> zeroinitializer, <vscale x 16 x i1> %6, i8 %7)
  store <vscale x 16 x i8> %8, ptr %5, align 16
  %9 = load <vscale x 16 x i8>, ptr %5, align 16
  ret <vscale x 16 x i8> %9
}
```