commit be31a7b7eec8ed7c033f3087dd88e8fd685c3ded
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Jan 10 11:02:18 2020 -0500
committer Matt Arsenault <arsenm2@gmail.com> Thu Jan 16 14:29:37 2020 -0500
tree 88191eb868b079a4c315d91e96b19391cb4e5533
parent 5f65065437cdbb680a6552d12d43090dc8d632b9

GlobalISel: Move extension scalar narrowing to separate function

Also rename a few things. Handling a different requested type will
require this to become much more complex.

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index daf4fad..2f9e977 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -219,6 +219,7 @@
   LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
 
   LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
+  LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
   LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
 
   LegalizeResult lowerBitcast(MachineInstr &MI);

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index f85dd76..1513f98 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -659,38 +659,8 @@
   }
   case TargetOpcode::G_SEXT:
   case TargetOpcode::G_ZEXT:
-  case TargetOpcode::G_ANYEXT: {
-    if (TypeIdx != 0)
-      return UnableToLegalize;
-
-    Register SrcReg = MI.getOperand(1).getReg();
-    LLT SrcTy = MRI.getType(SrcReg);
-    uint64_t SizeOp1 = SrcTy.getSizeInBits();
-    if (SizeOp0 % SizeOp1 != 0)
-      return UnableToLegalize;
-
-    Register PadReg;
-    if (MI.getOpcode() == TargetOpcode::G_ZEXT)
-      PadReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
-    else if (MI.getOpcode() == TargetOpcode::G_ANYEXT)
-      PadReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
-    else {
-      // Shift the sign bit of the low register through the high register.
-      auto ShiftAmt =
-        MIRBuilder.buildConstant(LLT::scalar(64), SrcTy.getSizeInBits() - 1);
-      PadReg = MIRBuilder.buildAShr(SrcTy, SrcReg, ShiftAmt).getReg(0);
-    }
-
-    // Generate a merge where the bottom bits are taken from the source, and
-    // zero/impdef/sign bit everything else.
-    unsigned NumParts = SizeOp0 / SizeOp1;
-    SmallVector<Register, 4> Srcs = {SrcReg};
-    for (unsigned Part = 1; Part < NumParts; ++Part)
-      Srcs.push_back(PadReg);
-    MIRBuilder.buildMerge(MI.getOperand(0), Srcs);
-    MI.eraseFromParent();
-    return Legalized;
-  }
+  case TargetOpcode::G_ANYEXT:
+    return narrowScalarExt(MI, TypeIdx, NarrowTy);
   case TargetOpcode::G_TRUNC: {
     if (TypeIdx != 1)
       return UnableToLegalize;
@@ -3681,6 +3651,45 @@
 }
 
 LegalizerHelper::LegalizeResult
+LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
+                                 LLT NarrowTy) {
+  if (TypeIdx != 0)
+    return UnableToLegalize;
+
+  Register DstReg = MI.getOperand(0).getReg();
+  Register SrcReg = MI.getOperand(1).getReg();
+  LLT DstTy = MRI.getType(DstReg);
+  LLT SrcTy = MRI.getType(SrcReg);
+  unsigned DstSize = DstTy.getSizeInBits();
+  unsigned SrcSize = SrcTy.getSizeInBits();
+
+  if (DstSize % SrcSize != 0)
+    return UnableToLegalize;
+
+  Register PadReg;
+  if (MI.getOpcode() == TargetOpcode::G_ZEXT)
+    PadReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
+  else if (MI.getOpcode() == TargetOpcode::G_ANYEXT)
+    PadReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
+  else {
+    // Shift the sign bit of the low register through the high register.
+    auto ShiftAmt =
+      MIRBuilder.buildConstant(LLT::scalar(64), SrcSize - 1);
+    PadReg = MIRBuilder.buildAShr(SrcTy, SrcReg, ShiftAmt).getReg(0);
+  }
+
+  // Generate a merge where the bottom bits are taken from the source, and
+  // zero/impdef/sign bit everything else.
+  unsigned NumParts = DstSize / SrcSize;
+  SmallVector<Register, 4> Srcs = {SrcReg};
+  for (unsigned Part = 1; Part < NumParts; ++Part)
+    Srcs.push_back(PadReg);
+  MIRBuilder.buildMerge(DstReg, Srcs);
+  MI.eraseFromParent();
+  return Legalized;
+}
+
+LegalizerHelper::LegalizeResult
 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
                                     LLT NarrowTy) {
   if (TypeIdx != 0)