[AMDGPU] Add subtarget feature for v_lshl_add_u64. NFC. (#133723)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 84619dd..6963b24 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -1269,6 +1269,10 @@
"Use a block size of 32 for dynamic VGPR allocation (default is 16)"
>;
+def FeatureLshlAddU64Inst
+ : SubtargetFeature<"lshl-add-u64-inst", "HasLshlAddU64Inst", "true",
+ "Has v_lshl_add_u64 instruction">;
+
// Dummy feature used to disable assembler instructions.
def FeatureDisable : SubtargetFeature<"",
"FeatureDisable","true",
@@ -1622,7 +1626,8 @@
FeatureAtomicFMinFMaxF64FlatInsts,
FeatureAgentScopeFineGrainedRemoteMemoryAtomics,
FeatureMemoryAtomicFAddF32DenormalSupport,
- FeatureFlatBufferGlobalAtomicFaddF64Inst
+ FeatureFlatBufferGlobalAtomicFaddF64Inst,
+ FeatureLshlAddU64Inst,
]>;
def FeatureISAVersion9_5_Common : FeatureSet<
@@ -2554,6 +2559,9 @@
def HasAshrPkInsts : Predicate<"Subtarget->hasAshrPkInsts()">,
AssemblerPredicate<(all_of FeatureAshrPkInsts)>;
+def HasLshlAddU64Inst : Predicate<"Subtarget->hasLshlAddU64Inst()">,
+ AssemblerPredicate<(all_of FeatureLshlAddU64Inst)>;
+
// Include AMDGPU TD files
include "SISchedule.td"
include "GCNProcessors.td"
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 7384278..301e4c0 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -257,6 +257,7 @@
bool HasMinimum3Maximum3F32 = false;
bool HasMinimum3Maximum3F16 = false;
bool HasMinimum3Maximum3PKF16 = false;
+ bool HasLshlAddU64Inst = false;
bool RequiresCOV6 = false;
@@ -1140,7 +1141,7 @@
bool hasMovB64() const { return GFX940Insts; }
- bool hasLshlAddB64() const { return GFX940Insts; }
+ bool hasLshlAddU64Inst() const { return HasLshlAddU64Inst; }
bool enableSIScheduler() const {
return EnableSIScheduler;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 56149bc..96c113c 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5246,7 +5246,7 @@
MachineOperand &Src0 = MI.getOperand(1);
MachineOperand &Src1 = MI.getOperand(2);
- if (IsAdd && ST.hasLshlAddB64()) {
+ if (IsAdd && ST.hasLshlAddU64Inst()) {
auto Add = BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_LSHL_ADD_U64_e64),
Dest.getReg())
.add(Src0)
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 14da344..9feb5df 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -679,7 +679,7 @@
// V_LSHL_ADD_U64: D0.u64 = (S0.u64 << S1.u[2:0]) + S2.u64
// src0 is shifted left by 0-4 (use “0” to get ADD_U64).
-let SubtargetPredicate = isGFX940Plus in
+let SubtargetPredicate = HasLshlAddU64Inst in
defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", VOP3_Profile<VOP_I64_I64_I32_I64>>;
let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
