)]}'
{
  "commit": "bd8578c3574d77bc1231f047bced4a0053a1b000",
  "tree": "d0065179ebb267b635b3f74d6fa2cf8c0463bfed",
  "parents": [
    "7a3b5d789d5fee6fe9883b6a3cb9d2ede4262276"
  ],
  "author": {
    "name": "hev",
    "email": "wangrui@loongson.cn",
    "time": "Thu May 22 18:49:27 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu May 22 18:49:27 2025 +0800"
  },
  "message": "[LoongArch] Prevent R0/R1 allocation for rj operand of [G]CSRXCHG (#140862)\n\nThe `[G]CSRXCHG` instruction must not use R0 or R1 as the `rj` operand,\nas encoding `rj` as 0 or 1 will be interpreted as `[G]CSRRD` OR\n`[G]CSRWR`, respectively, rather than `[G]CSRXCHG`.\n\nThis patch introduces a new register class `GPRNoR0R1` and updates the\n`[G]CSRXCHG` instruction definition to use it for the `rj` operand,\nensuring the register allocator avoids assigning R0 or R1.\n\nFixes #140842",
  "tree_diff": [
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    },
    {
      "type": "modify",
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}