[CodeGen][GlobalISel] Add a getVectorIdxWidth and getVectorIdxLLT. (#131526)
From #106446, this adds a variant of getVectorIdxTy that returns an LLT.
Many uses only look at the width, so a getVectorIdxWidth was added as
the common base.
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index b85239e..6014f57 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3174,7 +3174,7 @@
Register Res = getOrCreateVReg(U);
Register Val = getOrCreateVReg(*U.getOperand(0));
Register Elt = getOrCreateVReg(*U.getOperand(1));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
Register Idx;
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(2))) {
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3200,7 +3200,7 @@
Register Elt = getOrCreateVReg(*U.getOperand(1));
ConstantInt *CI = cast<ConstantInt>(U.getOperand(2));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
// Resize Index to preferred index width.
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3255,7 +3255,7 @@
Register Res = getOrCreateVReg(U);
Register Val = getOrCreateVReg(*U.getOperand(0));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
Register Idx;
if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
if (CI->getBitWidth() != PreferredVecIdxWidth) {
@@ -3279,7 +3279,7 @@
Register Res = getOrCreateVReg(U);
Register Vec = getOrCreateVReg(*U.getOperand(0));
ConstantInt *CI = cast<ConstantInt>(U.getOperand(1));
- unsigned PreferredVecIdxWidth = TLI->getVectorIdxTy(*DL).getSizeInBits();
+ unsigned PreferredVecIdxWidth = TLI->getVectorIdxWidth(*DL);
// Resize Index to preferred index width.
if (CI->getBitWidth() != PreferredVecIdxWidth) {
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index ed8bd25..622d6d0 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4229,7 +4229,7 @@
unsigned NumBits = MemTy.getSizeInBits();
LLT IntTy = LLT::scalar(NumBits);
auto CurrVal = MIRBuilder.buildConstant(IntTy, 0);
- LLT IdxTy = getLLTForMVT(TLI.getVectorIdxTy(MF.getDataLayout()));
+ LLT IdxTy = TLI.getVectorIdxLLT(MF.getDataLayout());
for (unsigned I = 0, E = MemTy.getNumElements(); I < E; ++I) {
auto Elt = MIRBuilder.buildExtractVectorElement(
@@ -6277,7 +6277,7 @@
auto NeutralElement = getNeutralElementForVecReduce(
MI.getOpcode(), MIRBuilder, MoreTy.getElementType());
- LLT IdxTy(TLI.getVectorIdxTy(MIRBuilder.getDataLayout()));
+ LLT IdxTy(TLI.getVectorIdxLLT(MIRBuilder.getDataLayout()));
for (size_t i = OrigTy.getNumElements(), e = MoreTy.getNumElements();
i != e; i++) {
auto Idx = MIRBuilder.buildConstant(IdxTy, i);
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 87d3033..b806790 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1993,8 +1993,7 @@
}
auto TLI = MF->getSubtarget().getTargetLowering();
- if (IdxTy.getSizeInBits() !=
- TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
+ if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
report("Index type must match VectorIdxTy", MI);
break;
}
@@ -2023,8 +2022,7 @@
}
auto TLI = MF->getSubtarget().getTargetLowering();
- if (IdxTy.getSizeInBits() !=
- TLI->getVectorIdxTy(MF->getDataLayout()).getFixedSizeInBits()) {
+ if (IdxTy.getSizeInBits() != TLI->getVectorIdxWidth(MF->getDataLayout())) {
report("Index type must match VectorIdxTy", MI);
break;
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 0b2d182..d1f92c9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -7549,7 +7549,7 @@
N1VT.getVectorMinNumElements()) &&
"Extract subvector overflow!");
assert(N2C->getAPIntValue().getBitWidth() ==
- TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
+ TLI->getVectorIdxWidth(getDataLayout()) &&
"Constant index for EXTRACT_SUBVECTOR has an invalid size");
// Trivial extraction.
@@ -7783,7 +7783,7 @@
VT.getVectorMinNumElements()) &&
"Insert subvector overflow!");
assert(N3->getAsAPIntVal().getBitWidth() ==
- TLI->getVectorIdxTy(getDataLayout()).getFixedSizeInBits() &&
+ TLI->getVectorIdxWidth(getDataLayout()) &&
"Constant index for INSERT_SUBVECTOR has an invalid size");
// Trivial insertion.