[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 80786c6..428355a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -428,8 +428,8 @@
void initializeSIFormMemoryClausesLegacyPass(PassRegistry &);
extern char &SIFormMemoryClausesID;
-void initializeSIPostRABundlerPass(PassRegistry&);
-extern char &SIPostRABundlerID;
+void initializeSIPostRABundlerLegacyPass(PassRegistry &);
+extern char &SIPostRABundlerLegacyID;
void initializeGCNCreateVOPDPass(PassRegistry &);
extern char &GCNCreateVOPDID;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
index a4504d7..e89d84c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPassRegistry.def
@@ -115,6 +115,7 @@
MACHINE_FUNCTION_PASS("si-optimize-exec-masking", SIOptimizeExecMaskingPass())
MACHINE_FUNCTION_PASS("si-optimize-exec-masking-pre-ra", SIOptimizeExecMaskingPreRAPass())
MACHINE_FUNCTION_PASS("si-peephole-sdwa", SIPeepholeSDWAPass())
+MACHINE_FUNCTION_PASS("si-post-ra-bundler", SIPostRABundlerPass())
MACHINE_FUNCTION_PASS("si-pre-allocate-wwm-regs", SIPreAllocateWWMRegsPass())
MACHINE_FUNCTION_PASS("si-shrink-instructions", SIShrinkInstructionsPass())
MACHINE_FUNCTION_PASS("si-wqm", SIWholeQuadModePass())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index dbd126d..828c170 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -54,6 +54,7 @@
#include "SIOptimizeExecMaskingPreRA.h"
#include "SIOptimizeVGPRLiveRange.h"
#include "SIPeepholeSDWA.h"
+#include "SIPostRABundler.h"
#include "SIPreAllocateWWMRegs.h"
#include "SIShrinkInstructions.h"
#include "SIWholeQuadMode.h"
@@ -544,7 +545,7 @@
initializeSIOptimizeExecMaskingLegacyPass(*PR);
initializeSIPreAllocateWWMRegsLegacyPass(*PR);
initializeSIFormMemoryClausesLegacyPass(*PR);
- initializeSIPostRABundlerPass(*PR);
+ initializeSIPostRABundlerLegacyPass(*PR);
initializeGCNCreateVOPDPass(*PR);
initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
initializeAMDGPUAAWrapperPassPass(*PR);
@@ -1658,7 +1659,7 @@
void GCNPassConfig::addPreSched2() {
if (TM->getOptLevel() > CodeGenOptLevel::None)
addPass(createSIShrinkInstructionsLegacyPass());
- addPass(&SIPostRABundlerID);
+ addPass(&SIPostRABundlerLegacyID);
}
void GCNPassConfig::addPreEmitPass() {
diff --git a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
index 8464cb3..87ff4b4 100644
--- a/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPostRABundler.cpp
@@ -12,6 +12,7 @@
///
//===----------------------------------------------------------------------===//
+#include "SIPostRABundler.h"
#include "AMDGPU.h"
#include "GCNSubtarget.h"
#include "llvm/ADT/SmallSet.h"
@@ -23,13 +24,13 @@
namespace {
-class SIPostRABundler : public MachineFunctionPass {
+class SIPostRABundlerLegacy : public MachineFunctionPass {
public:
static char ID;
public:
- SIPostRABundler() : MachineFunctionPass(ID) {
- initializeSIPostRABundlerPass(*PassRegistry::getPassRegistry());
+ SIPostRABundlerLegacy() : MachineFunctionPass(ID) {
+ initializeSIPostRABundlerLegacyPass(*PassRegistry::getPassRegistry());
}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -42,6 +43,11 @@
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
}
+};
+
+class SIPostRABundler {
+public:
+ bool run(MachineFunction &MF);
private:
const SIRegisterInfo *TRI;
@@ -62,14 +68,15 @@
} // End anonymous namespace.
-INITIALIZE_PASS(SIPostRABundler, DEBUG_TYPE, "SI post-RA bundler", false, false)
+INITIALIZE_PASS(SIPostRABundlerLegacy, DEBUG_TYPE, "SI post-RA bundler", false,
+ false)
-char SIPostRABundler::ID = 0;
+char SIPostRABundlerLegacy::ID = 0;
-char &llvm::SIPostRABundlerID = SIPostRABundler::ID;
+char &llvm::SIPostRABundlerLegacyID = SIPostRABundlerLegacy::ID;
FunctionPass *llvm::createSIPostRABundlerPass() {
- return new SIPostRABundler();
+ return new SIPostRABundlerLegacy();
}
bool SIPostRABundler::isDependentLoad(const MachineInstr &MI) const {
@@ -121,9 +128,19 @@
!isDependentLoad(NextMI));
}
-bool SIPostRABundler::runOnMachineFunction(MachineFunction &MF) {
+bool SIPostRABundlerLegacy::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
+ return SIPostRABundler().run(MF);
+}
+
+PreservedAnalyses SIPostRABundlerPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &) {
+ SIPostRABundler().run(MF);
+ return PreservedAnalyses::all();
+}
+
+bool SIPostRABundler::run(MachineFunction &MF) {
TRI = MF.getSubtarget<GCNSubtarget>().getRegisterInfo();
BitVector BundleUsedRegUnits(TRI->getNumRegUnits());
diff --git a/llvm/lib/Target/AMDGPU/SIPostRABundler.h b/llvm/lib/Target/AMDGPU/SIPostRABundler.h
new file mode 100644
index 0000000..2038bbe
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/SIPostRABundler.h
@@ -0,0 +1,22 @@
+//===- SIPostRABundler.h ----------------------------------------*- C++- *-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H
+#define LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H
+
+#include "llvm/CodeGen/MachinePassManager.h"
+
+namespace llvm {
+class SIPostRABundlerPass : public PassInfoMixin<SIPostRABundlerPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+} // namespace llvm
+
+#endif // LLVM_LIB_TARGET_AMDGPU_SIPOSTRABUNDLER_H
diff --git a/llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir b/llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
index b878ee5..458afca 100644
--- a/llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
+++ b/llvm/test/CodeGen/AMDGPU/postra-bundle-memops.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-post-ra-bundler %s -o - | FileCheck -check-prefix=GCN %s
+# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -passes=si-post-ra-bundler %s -o - | FileCheck -check-prefix=GCN %s
---
name: bundle_memops
