; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s

declare <512 x float> @llvm.masked.load.v512f32.p0(ptr %0, i32 immarg %1, <512 x i1> %2, <512 x float> %3) #0

; Function Attrs: nounwind
define fastcc <512 x float> @vec_mload_v512f32(ptr %P, <512 x i1> %M) {
; CHECK-LABEL: vec_mload_v512f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lea %s1, 256
; CHECK-NEXT:    lvl %s1
; CHECK-NEXT:    vldu %v0, 8, %s0
; CHECK-NEXT:    lea %s0, 4(, %s0)
; CHECK-NEXT:    vldu %v1, 8, %s0
; CHECK-NEXT:    vshf %v0, %v1, %v0, 8
; CHECK-NEXT:    b.l.t (, %s10)
  %r = call <512 x float> @llvm.masked.load.v512f32.p0(ptr %P, i32 16, <512 x i1> %M, <512 x float> undef)
  ret <512 x float> %r
}

; TODO: Packed select legalization
; Function Attrs: nounwind
; define fastcc <512 x float> @vec_mload_pt_v512f32(ptr %P, <512 x float> %PT, <512 x i1> %M) {
;   %r = call <512 x float> @llvm.masked.load.v512f32.p0(ptr %P, i32 16, <512 x i1> %M, <512 x float> %PT)
;   ret <512 x float> %r
; }

declare <512 x i32> @llvm.masked.load.v512i32.p0(ptr %0, i32 immarg %1, <512 x i1> %2, <512 x i32> %3) #0

; Function Attrs: nounwind
define fastcc <512 x i32> @vec_mload_v512i32(ptr %P, <512 x i1> %M) {
; CHECK-LABEL: vec_mload_v512i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lea %s1, 256
; CHECK-NEXT:    lvl %s1
; CHECK-NEXT:    vldl.zx %v0, 8, %s0
; CHECK-NEXT:    lea %s0, 4(, %s0)
; CHECK-NEXT:    vldl.zx %v1, 8, %s0
; CHECK-NEXT:    vshf %v0, %v1, %v0, 13
; CHECK-NEXT:    b.l.t (, %s10)
  %r = call <512 x i32> @llvm.masked.load.v512i32.p0(ptr %P, i32 16, <512 x i1> %M, <512 x i32> undef)
  ret <512 x i32> %r
}

; TODO: Packed select legalization
; ; Function Attrs: nounwind
; define fastcc <512 x i32> @vec_mload_pt_v512i32(ptr %P, <512 x i32> %PT, <512 x i1> %M) {
;   %r = call <512 x i32> @llvm.masked.load.v512i32.p0(ptr %P, i32 16, <512 x i1> %M, <512 x i32> %PT)
;   ret <512 x i32> %r
; }

attributes #0 = { argmemonly nounwind readonly willreturn }