; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-SDAG %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9-GISEL %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISEL %s

define amdgpu_kernel void @flat_atomic_usub_cond_no_rtn_u32(ptr %addr, i32 %in) {
; GFX9-SDAG-LABEL: flat_atomic_usub_cond_no_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_add_u32 s0, s0, -16
; GFX9-SDAG-NEXT:    s_addc_u32 s1, s1, -1
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-SDAG-NEXT:    flat_load_dword v3, v[0:1]
; GFX9-SDAG-NEXT:    s_mov_b64 s[0:1], 0
; GFX9-SDAG-NEXT:  .LBB0_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v2, s2, v3
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-SDAG-NEXT:    flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-SDAG-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v3, v2
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB0_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: flat_atomic_usub_cond_no_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], -16
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v2, s2
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    flat_atomic_cond_sub_u32 v[0:1], v2 scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt_dscnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: flat_atomic_usub_cond_no_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s2, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_add_u32 s0, s0, -16
; GFX9-GISEL-NEXT:    s_addc_u32 s1, s1, -1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s1
; GFX9-GISEL-NEXT:    flat_load_dword v3, v[0:1]
; GFX9-GISEL-NEXT:    s_mov_b64 s[0:1], 0
; GFX9-GISEL-NEXT:  .LBB0_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v2, s2, v3
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-GISEL-NEXT:    flat_atomic_cmpswap v2, v[0:1], v[2:3] glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v3
; GFX9-GISEL-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, v2
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB0_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: flat_atomic_usub_cond_no_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_add_co_u32 s0, s0, -16
; GFX12-GISEL-NEXT:    s_add_co_ci_u32 s1, s1, -1
; GFX12-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v2, s2
; GFX12-GISEL-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    flat_atomic_cond_sub_u32 v[0:1], v2 scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt_dscnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr %addr, i32 -4
  %unused = atomicrmw usub_cond ptr %gep, i32 %in seq_cst, !amdgpu.no.remote.memory !0
  ret void
}

define amdgpu_kernel void @flat_atomic_usub_cond_rtn_u32(ptr %addr, i32 %in, ptr %use) {
; GFX9-SDAG-LABEL: flat_atomic_usub_cond_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_add_u32 s2, s0, 16
; GFX9-SDAG-NEXT:    s_addc_u32 s3, s1, 0
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s2
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s3
; GFX9-SDAG-NEXT:    flat_load_dword v0, v[0:1]
; GFX9-SDAG-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-SDAG-NEXT:  .LBB1_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-SDAG-NEXT:    s_add_u32 s8, s0, 16
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-SDAG-NEXT:    s_addc_u32 s9, s1, 0
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, s8
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v3, s9
; GFX9-SDAG-NEXT:    flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB1_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, s1
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s0
; GFX9-SDAG-NEXT:    flat_store_dword v[1:2], v0
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: flat_atomic_usub_cond_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_clause 0x1
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_add_nc_u64 s[0:1], s[0:1], 16
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v2, s2
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    flat_atomic_cond_sub_u32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-SDAG-NEXT:    flat_store_b32 v[0:1], v2
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: flat_atomic_usub_cond_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_add_u32 s2, s0, 16
; GFX9-GISEL-NEXT:    s_addc_u32 s3, s1, 0
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s2
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s3
; GFX9-GISEL-NEXT:    flat_load_dword v0, v[0:1]
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:  .LBB1_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-GISEL-NEXT:    s_add_u32 s8, s0, 16
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-GISEL-NEXT:    s_addc_u32 s9, s1, 0
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s8
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v3, s9
; GFX9-GISEL-NEXT:    flat_atomic_cmpswap v0, v[2:3], v[0:1] glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB1_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, s1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s0
; GFX9-GISEL-NEXT:    flat_store_dword v[1:2], v0
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: flat_atomic_usub_cond_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_clause 0x1
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_add_co_u32 s0, s0, 16
; GFX12-GISEL-NEXT:    s_add_co_ci_u32 s1, s1, 0
; GFX12-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v2, s2
; GFX12-GISEL-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    flat_atomic_cond_sub_u32 v2, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX12-GISEL-NEXT:    flat_store_b32 v[0:1], v2
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr %addr, i32 4
  %val = atomicrmw usub_cond ptr %gep, i32 %in seq_cst, !amdgpu.no.remote.memory !0
  store i32 %val, ptr %use
  ret void
}

define amdgpu_kernel void @global_atomic_usub_cond_no_rtn_u32(ptr addrspace(1) %addr, i32 %in) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_no_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_add_u32 s2, s0, -16
; GFX9-SDAG-NEXT:    s_addc_u32 s3, s1, -1
; GFX9-SDAG-NEXT:    s_load_dword s4, s[2:3], 0x0
; GFX9-SDAG-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-SDAG-NEXT:  .LBB2_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v0, v2, v[0:1], s[0:1] offset:-16 glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB2_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_no_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-SDAG-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v1, s[0:1] offset:-16 scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_no_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_add_u32 s2, s0, -16
; GFX9-GISEL-NEXT:    s_addc_u32 s3, s1, -1
; GFX9-GISEL-NEXT:    s_load_dword s4, s[2:3], 0x0
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-GISEL-NEXT:  .LBB2_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v0, v2, v[0:1], s[0:1] offset:-16 glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB2_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_no_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v1, v0, s[0:1] offset:-16 scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(1) %addr, i32 -4
  %unused = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %in seq_cst, !amdgpu.no.remote.memory !0
  ret void
}

define amdgpu_kernel void @global_atomic_usub_cond_rtn_u32(ptr addrspace(1) %addr, i32 %in, ptr addrspace(1) %use) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_load_dword s7, s[0:1], 0x10
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s7
; GFX9-SDAG-NEXT:  .LBB3_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v1, s6, v2
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v1, v0, v[1:2], s[0:1] offset:16 glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB3_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX12-SDAG-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v1, v0, v1, s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-SDAG-NEXT:    global_store_b32 v0, v1, s[4:5]
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_load_dword s7, s[0:1], 0x10
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s7
; GFX9-GISEL-NEXT:  .LBB3_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v1, s6, v2
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v1, v0, v[1:2], s[0:1] offset:16 glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB3_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_clause 0x1
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    global_wb scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v1, v0, s[0:1] offset:16 th:TH_ATOMIC_RETURN scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SYS
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[4:5]
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(1) %addr, i32 4
  %val = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %in seq_cst, !amdgpu.no.remote.memory !0
  store i32 %val, ptr addrspace(1) %use
  ret void
}

define amdgpu_kernel void @ds_usub_cond_no_rtn_u32(ptr addrspace(3) %addr, i32 %in) {
; GFX9-SDAG-LABEL: ds_usub_cond_no_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_add_i32 s0, s0, -16
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-SDAG-NEXT:    ds_read_b32 v1, v0
; GFX9-SDAG-NEXT:  .LBB4_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v2, s1, v1
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s1, v1
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX9-SDAG-NEXT:    ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v2
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB4_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: ds_usub_cond_no_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_add_co_i32 s0, s0, -16
; GFX12-SDAG-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX12-SDAG-NEXT:    ds_cond_sub_u32 v0, v1
; GFX12-SDAG-NEXT:    s_wait_dscnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SE
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: ds_usub_cond_no_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_add_u32 s0, s0, -16
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT:    ds_read_b32 v1, v0
; GFX9-GISEL-NEXT:  .LBB4_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v2, s1, v1
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s1, v1
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v2, v1, v2, vcc
; GFX9-GISEL-NEXT:    ds_cmpst_rtn_b32 v2, v0, v1, v2
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v2, v1
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v2
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB4_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: ds_usub_cond_no_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_add_co_u32 s0, s0, -16
; GFX12-GISEL-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v0, s0
; GFX12-GISEL-NEXT:    ds_cond_sub_u32 v0, v1
; GFX12-GISEL-NEXT:    s_wait_dscnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SE
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(3) %addr, i32 -4
  %unused = atomicrmw usub_cond ptr addrspace(3) %gep, i32 %in seq_cst
  ret void
}

define amdgpu_kernel void @ds_usub_cond_rtn_u32(ptr addrspace(3) %addr, i32 %in, ptr addrspace(3) %use) {
; GFX9-SDAG-LABEL: ds_usub_cond_rtn_u32:
; GFX9-SDAG:       ; %bb.0: ; %entry
; GFX9-SDAG-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-SDAG-NEXT:    ds_read_b32 v1, v0 offset:16
; GFX9-SDAG-NEXT:  .LBB5_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v1, s1, v2
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s1, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-SDAG-NEXT:    ds_cmpst_rtn_b32 v1, v0, v2, v1 offset:16
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB5_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, s2
; GFX9-SDAG-NEXT:    ds_write_b32 v0, v1
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: ds_usub_cond_rtn_u32:
; GFX12-SDAG:       ; %bb.0: ; %entry
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX12-SDAG-NEXT:    ds_cond_sub_rtn_u32 v0, v0, v1 offset:16
; GFX12-SDAG-NEXT:    s_wait_dscnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_SE
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT:    ds_store_b32 v1, v0
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: ds_usub_cond_rtn_u32:
; GFX9-GISEL:       ; %bb.0: ; %entry
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s0
; GFX9-GISEL-NEXT:    ds_read_b32 v1, v0 offset:16
; GFX9-GISEL-NEXT:  .LBB5_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v1, s1, v2
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s1, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-GISEL-NEXT:    ds_cmpst_rtn_b32 v1, v0, v2, v1 offset:16
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB5_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, s6
; GFX9-GISEL-NEXT:    ds_write_b32 v0, v1
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: ds_usub_cond_rtn_u32:
; GFX12-GISEL:       ; %bb.0: ; %entry
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX12-GISEL-NEXT:    ds_cond_sub_rtn_u32 v0, v1, v0 offset:16
; GFX12-GISEL-NEXT:    s_wait_dscnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_SE
; GFX12-GISEL-NEXT:    v_mov_b32_e32 v1, s2
; GFX12-GISEL-NEXT:    ds_store_b32 v1, v0
; GFX12-GISEL-NEXT:    s_endpgm
entry:
  %gep = getelementptr i32, ptr addrspace(3) %addr, i32 4
  %val = atomicrmw usub_cond ptr addrspace(3) %gep, i32 %in seq_cst, !amdgpu.no.remote.memory !0
  store i32 %val, ptr addrspace(3) %use
  ret void
}

define i32 @global_atomic_usub_cond(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB6_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB6_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB6_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB6_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %ret = atomicrmw usub_cond ptr addrspace(1) %ptr, i32 %data syncscope("agent") seq_cst, align 4
  ret i32 %ret
}

define i32 @global_atomic_usub_cond_offset(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_offset:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v3, vcc, 0x1000, v0
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], vcc
; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v4, s[4:5], 0, v1, s[4:5]
; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    global_load_dword v0, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB7_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v0, v1, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v0, v[3:4], v[0:1], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB7_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_offset:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off offset:4096 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_offset:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v3, vcc, 0x1000, v0
; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v4, vcc, 0, v1, vcc
; GFX9-GISEL-NEXT:    global_load_dword v0, v[3:4], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB7_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v0, v1, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v0, v[3:4], v[0:1], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB7_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_offset:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off offset:4096 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 1024
  %ret = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %data syncscope("agent") seq_cst, align 4
  ret i32 %ret
}

define void @global_atomic_usub_cond_nortn(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_nortn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_load_dword v4, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB8_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB8_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_nortn:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v[0:1], v2, off scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_nortn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_load_dword v4, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB8_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB8_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_nortn:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v[0:1], v2, off scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %ret = atomicrmw usub_cond ptr addrspace(1) %ptr, i32 %data syncscope("agent") seq_cst, align 4
  ret void
}

define void @global_atomic_usub_cond_offset_nortn(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_offset_nortn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_add_co_u32_e32 v3, vcc, 0x1000, v0
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], vcc
; GFX9-SDAG-NEXT:    v_addc_co_u32_e64 v4, s[4:5], 0, v1, s[4:5]
; GFX9-SDAG-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    global_load_dword v1, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB9_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v0, v1, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v0, v[3:4], v[0:1], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB9_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_offset_nortn:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v[0:1], v2, off offset:4096 scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_offset_nortn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
; GFX9-GISEL-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-GISEL-NEXT:    global_load_dword v4, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB9_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB9_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_offset_nortn:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v[0:1], v2, off offset:4096 scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 1024
  %ret = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %data syncscope("agent") seq_cst, align 4
  ret void
}

define amdgpu_kernel void @global_atomic_usub_cond_sgpr_base_offset(ptr addrspace(1) %ptr, i32 %data, ptr addrspace(1) %dst) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_sgpr_base_offset:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_mov_b64 s[0:1], 0
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_load_dword s7, s[2:3], 0x1000
; GFX9-SDAG-NEXT:    s_add_u32 s2, s2, 0x1000
; GFX9-SDAG-NEXT:    s_addc_u32 s3, s3, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s7
; GFX9-SDAG-NEXT:  .LBB10_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v1, s6, v2
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v1, v0, v[1:2], s[2:3] glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-SDAG-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB10_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_sgpr_base_offset:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX12-SDAG-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_mov_b32_e32 v1, s2
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v1, v0, v1, s[0:1] offset:4096 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    global_store_b32 v0, v1, s[4:5]
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_sgpr_base_offset:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, 0x1000
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_load_dword s7, s[0:1], 0x1000
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s7
; GFX9-GISEL-NEXT:  .LBB10_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, v1
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v1, s6, v2
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v1, v0, v[1:2], s[0:1] glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v1, v2
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB10_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, 0
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_sgpr_base_offset:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_clause 0x1
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_load_b64 s[4:5], s[4:5], 0x34
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v1, v0, s[0:1] offset:4096 th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    global_store_b32 v1, v0, s[4:5]
; GFX12-GISEL-NEXT:    s_endpgm
  %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 1024
  %ret = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %data syncscope("agent") seq_cst, align 4
  store i32 %ret, ptr addrspace(1) %dst
  ret void
}

define amdgpu_kernel void @global_atomic_usub_cond_sgpr_base_offset_nortn(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond_sgpr_base_offset_nortn:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_load_dwordx2 s[2:3], s[4:5], 0x24
; GFX9-SDAG-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-SDAG-NEXT:    s_mov_b64 s[0:1], 0
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v2, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    s_load_dword s4, s[2:3], 0x1000
; GFX9-SDAG-NEXT:    s_add_u32 s2, s2, 0x1000
; GFX9-SDAG-NEXT:    s_addc_u32 s3, s3, 0
; GFX9-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-SDAG-NEXT:  .LBB11_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-SDAG-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v0, v2, v[0:1], s[2:3] glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-SDAG-NEXT:    s_or_b64 s[0:1], vcc, s[0:1]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB11_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_endpgm
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond_sgpr_base_offset_nortn:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v1, s[0:1] offset:4096 scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_endpgm
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond_sgpr_base_offset_nortn:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-GISEL-NEXT:    s_load_dword s6, s[4:5], 0x2c
; GFX9-GISEL-NEXT:    s_mov_b64 s[2:3], 0
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v2, 0x1000
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x1000
; GFX9-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, s4
; GFX9-GISEL-NEXT:  .LBB11_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    v_subrev_u32_e32 v0, s6, v1
; GFX9-GISEL-NEXT:    v_cmp_le_u32_e32 vcc, s6, v1
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v0, v2, v[0:1], s[0:1] glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v0, v1
; GFX9-GISEL-NEXT:    s_or_b64 s[2:3], vcc, s[2:3]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v1, v0
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[2:3]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB11_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_endpgm
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond_sgpr_base_offset_nortn:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v1, v0, s[0:1] offset:4096 scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_endpgm
  %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 1024
  %ret = atomicrmw usub_cond ptr addrspace(1) %gep, i32 %data syncscope("agent") seq_cst, align 4
  ret void
}

define i32 @global_atomic_usub_cond__amdgpu_no_remote_memory(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_remote_memory:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB12_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB12_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_remote_memory:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_remote_memory:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB12_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB12_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_remote_memory:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %ret = atomicrmw usub_cond ptr addrspace(1) %ptr, i32 %data syncscope("agent") seq_cst, align 4, !amdgpu.no.remote.memory !0
  ret i32 %ret
}

define i32 @global_atomic_usub_cond__amdgpu_no_fine_grained_memory(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB13_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB13_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB13_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB13_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %ret = atomicrmw usub_cond ptr addrspace(1) %ptr, i32 %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0
  ret i32 %ret
}

define i32 @global_atomic_usub_cond__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory(ptr addrspace(1) %ptr, i32 %data) {
; GFX9-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX9-SDAG:       ; %bb.0:
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-SDAG-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-SDAG-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-SDAG-NEXT:  .LBB14_1: ; %atomicrmw.start
; GFX9-SDAG-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-SDAG-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-SDAG-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-SDAG-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-SDAG-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-SDAG-NEXT:    s_waitcnt vmcnt(0)
; GFX9-SDAG-NEXT:    buffer_wbinvl1_vol
; GFX9-SDAG-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-SDAG-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-SDAG-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    s_cbranch_execnz .LBB14_1
; GFX9-SDAG-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-SDAG-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-SDAG-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-SDAG-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX12-SDAG:       ; %bb.0:
; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0
; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0
; GFX12-SDAG-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_wait_loadcnt 0x0
; GFX12-SDAG-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX9-GISEL:       ; %bb.0:
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-GISEL-NEXT:    global_load_dword v3, v[0:1], off
; GFX9-GISEL-NEXT:    s_mov_b64 s[4:5], 0
; GFX9-GISEL-NEXT:  .LBB14_1: ; %atomicrmw.start
; GFX9-GISEL-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v4, v3
; GFX9-GISEL-NEXT:    v_sub_u32_e32 v3, v4, v2
; GFX9-GISEL-NEXT:    v_cmp_ge_u32_e32 vcc, v4, v2
; GFX9-GISEL-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-GISEL-NEXT:    global_atomic_cmpswap v3, v[0:1], v[3:4], off glc
; GFX9-GISEL-NEXT:    s_waitcnt vmcnt(0)
; GFX9-GISEL-NEXT:    buffer_wbinvl1_vol
; GFX9-GISEL-NEXT:    v_cmp_eq_u32_e32 vcc, v3, v4
; GFX9-GISEL-NEXT:    s_or_b64 s[4:5], vcc, s[4:5]
; GFX9-GISEL-NEXT:    s_andn2_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    s_cbranch_execnz .LBB14_1
; GFX9-GISEL-NEXT:  ; %bb.2: ; %atomicrmw.end
; GFX9-GISEL-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX9-GISEL-NEXT:    v_mov_b32_e32 v0, v3
; GFX9-GISEL-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-GISEL-LABEL: global_atomic_usub_cond__amdgpu_no_fine_grained_memory__amdgpu_no_remote_memory:
; GFX12-GISEL:       ; %bb.0:
; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0
; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0
; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0
; GFX12-GISEL-NEXT:    global_atomic_cond_sub_u32 v0, v[0:1], v2, off th:TH_ATOMIC_RETURN scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_wait_loadcnt 0x0
; GFX12-GISEL-NEXT:    global_inv scope:SCOPE_DEV
; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]
  %ret = atomicrmw usub_cond ptr addrspace(1) %ptr, i32 %data syncscope("agent") seq_cst, align 4, !amdgpu.no.fine.grained.memory !0, !amdgpu.no.remote.memory !0
  ret i32 %ret
}

attributes #0 = { nounwind willreturn }
attributes #1 = { argmemonly nounwind }

!0 = !{}