RISC-V: builtins support for MIPS RV64 P8700 execution control .
the following changes are made
a)Typo Fix (with previous PRhttps://github.com/llvm/llvm-project/pull/155747)
b)builtins support for MIPS P8700 execution control instructions .
c)Testcase
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td b/clang/include/clang/Basic/BuiltinsRISCV.td
index 5927eaf..2dad5ed 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -162,3 +162,8 @@
// XAndes extensions.
//===----------------------------------------------------------------------===//
include "clang/Basic/BuiltinsRISCVXAndes.td"
+
+//===----------------------------------------------------------------------===//
+// MIPS extensions.
+//===----------------------------------------------------------------------===//
+include "clang/Basic/BuiltinsRISCVXMIPS.td"
diff --git a/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td
new file mode 100644
index 0000000..07fb68a
--- /dev/null
+++ b/clang/include/clang/Basic/BuiltinsRISCVXMIPS.td
@@ -0,0 +1,21 @@
+//==- BuiltinsRISCVXMIPS.td - RISC-V MIPS Builtin database ----*- C++ -*-==//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the MIPS-specific builtin function database. Users of
+// this file must define the BUILTIN macro to make use of this information.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// MIPS execution control extensions.
+//===----------------------------------------------------------------------===//
+let Attributes = [NoThrow, Const] in {
+def mips_pause : RISCVBuiltin<"void()", "xmipsexectl">;
+def mips_ehb : RISCVBuiltin<"void()", "xmipsexectl">;
+def mips_ihb : RISCVBuiltin<"void()", "xmipsexectl">;
+}
diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt
index dd52498..32a6be8 100644
--- a/clang/lib/Headers/CMakeLists.txt
+++ b/clang/lib/Headers/CMakeLists.txt
@@ -131,6 +131,7 @@
riscv_ntlh.h
sifive_vector.h
andes_vector.h
+ riscv_mips.h
)
set(spirv_files
diff --git a/clang/lib/Headers/riscv_mips.h b/clang/lib/Headers/riscv_mips.h
new file mode 100644
index 0000000..124a989
--- /dev/null
+++ b/clang/lib/Headers/riscv_mips.h
@@ -0,0 +1,34 @@
+//===----- riscv_mips.h - RISC-V MIPS Intrinsic definitions
+//----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef __RISCV_MIPS_H
+#define __RISCV_MIPS_H
+
+#if !defined(__riscv)
+#error "This header is only meant to be used on riscv architecture"
+#endif
+
+#define __DEFAULT_FN_ATTRS \
+ __attribute__((__always_inline__, __nodebug__, __target__("xmipsexectl")))
+
+static __inline__ void __DEFAULT_FN_ATTRS __mips_pause() {
+ __builtin_riscv_mips_pause();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS __mips_ehb() {
+ __builtin_riscv_mips_ehb();
+}
+
+static __inline__ void __DEFAULT_FN_ATTRS __mips_ihb() {
+ __builtin_riscv_mips_ihb();
+}
+
+#undef __DEFAULT_FN_ATTRS
+
+#endif
diff --git a/clang/test/CodeGen/RISCV/builtins-riscv-mips.c b/clang/test/CodeGen/RISCV/builtins-riscv-mips.c
new file mode 100644
index 0000000..b20ab80
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/builtins-riscv-mips.c
@@ -0,0 +1,37 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
+// RUN: %clang_cc1 -triple riscv32-linux-elf -O3 -target-feature +xmipsexectl -emit-llvm -o - %s | FileCheck %s
+
+#include<riscv_mips.h>
+
+// CHECK-LABEL: define dso_local void @test_mips_pause(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: tail call void @llvm.riscv.mips.pause()
+// CHECK-NEXT: ret void
+//
+void test_mips_pause()
+{
+ __mips_pause();
+}
+
+// CHECK-LABEL: define dso_local void @test_mips_ehb(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: tail call void @llvm.riscv.mips.ehb()
+// CHECK-NEXT: ret void
+//
+void test_mips_ehb()
+{
+ __mips_ehb();
+}
+
+// CHECK-LABEL: define dso_local void @test_mips_ihb(
+// CHECK-SAME: ) local_unnamed_addr #[[ATTR0]] {
+// CHECK-NEXT: [[ENTRY:.*:]]
+// CHECK-NEXT: tail call void @llvm.riscv.mips.ihb()
+// CHECK-NEXT: ret void
+//
+void test_mips_ihb()
+{
+ __mips_ihb();
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 4d0debd..77fcc46 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1964,3 +1964,4 @@
include "llvm/IR/IntrinsicsRISCVXsf.td"
include "llvm/IR/IntrinsicsRISCVXCV.td"
include "llvm/IR/IntrinsicsRISCVXAndes.td"
+include "llvm/IR/IntrinsicsRISCVXMIPS.td"
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td
new file mode 100644
index 0000000..d231feb
--- /dev/null
+++ b/llvm/include/llvm/IR/IntrinsicsRISCVXMIPS.td
@@ -0,0 +1,20 @@
+//===- IntrinsicsRISCVXMIPS.td - MIPS intrinsics -------*- tablegen -*----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines all of the MIPS specific intrinsics for RISC-V.
+//
+//===----------------------------------------------------------------------===//
+
+let TargetPrefix = "riscv" in {
+ def int_riscv_mips_pause : ClangBuiltin<"__builtin_riscv_mips_pause">,
+ Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+ def int_riscv_mips_ehb : ClangBuiltin<"__builtin_riscv_mips_ehb">,
+ Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+ def int_riscv_mips_ihb : ClangBuiltin<"__builtin_riscv_mips_ihb">,
+ Intrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 8425cfb..677d935 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1439,7 +1439,7 @@
def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS execution control">;
def HasVendorXMIPSEXECTL
- : Predicate<"Subtarget->hasVendorXMIPSEXT()">,
+ : Predicate<"Subtarget->hasVendorXMIPSEXECTL()">,
AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),
"'Xmipsexectl' (MIPS execution control)">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
index d615094..115ab38e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -143,6 +143,13 @@
def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;
}
+let Predicates = [HasVendorXMIPSEXECTL] in {
+ // Intrinsics
+ def : Pat<(int_riscv_mips_pause), (MIPS_PAUSE)>;
+ def : Pat<(int_riscv_mips_ihb), (MIPS_IHB)>;
+ def : Pat<(int_riscv_mips_ehb), (MIPS_EHB)>;
+}
+
let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
"mips.pref", "$hint, ${imm9}(${rs1})">,
diff --git a/llvm/test/CodeGen/RISCV/xmips-exectl.ll b/llvm/test/CodeGen/RISCV/xmips-exectl.ll
new file mode 100644
index 0000000..a013e01
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/xmips-exectl.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -O3 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=MIPS %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"
+
+define void @test_mips_pause() {
+; MIPS-LABEL: test_mips_pause:
+; MIPS: # %bb.0: # %entry
+; MIPS-NEXT: mips.pause
+; MIPS-NEXT: ret
+entry:
+ tail call void @llvm.riscv.mips.pause()
+ ret void
+}
+
+define void @test_mips_ehb() {
+; MIPS-LABEL: test_mips_ehb:
+; MIPS: # %bb.0: # %entry
+; MIPS-NEXT: mips.ehb
+; MIPS-NEXT: ret
+entry:
+ tail call void @llvm.riscv.mips.ehb()
+ ret void
+}
+
+define void @test_mips_ihb() {
+; MIPS-LABEL: test_mips_ihb:
+; MIPS: # %bb.0: # %entry
+; MIPS-NEXT: mips.ihb
+; MIPS-NEXT: ret
+entry:
+ tail call void @llvm.riscv.mips.ihb()
+ ret void
+}
