# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops -arm-enable-subreg-liveness %s -o - --verify-machineinstrs | FileCheck %s

--- |
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv8.1m.main-arm-none-eabi"

  define i32 @test(i8* nocapture readnone %x, i32* noalias %y, i32 %n, <4 x i32> %0, <4 x i32> %1, <4 x i32> %2, <4 x i32> %3, <4 x i32> %p) {
  entry:
    %cmp13 = icmp sgt i32 %n, 0
    br i1 %cmp13, label %while.body.preheader, label %while.end

  while.body.preheader:                             ; preds = %entry
    %4 = add i32 %n, 3
    %smin = call i32 @llvm.smin.i32(i32 %n, i32 4)
    %5 = sub i32 %4, %smin
    %6 = lshr i32 %5, 2
    %7 = add nuw nsw i32 %6, 1
    %8 = call i32 @llvm.start.loop.iterations.i32(i32 %7)
    br label %while.body

  while.body:                                       ; preds = %while.body.preheader, %while.body
    %y.addr.016 = phi i32* [ %add.ptr, %while.body ], [ %y, %while.body.preheader ]
    %s.015 = phi <4 x i32> [ %mul, %while.body ], [ <i32 1, i32 1, i32 1, i32 1>, %while.body.preheader ]
    %n.addr.014 = phi i32 [ %12, %while.body ], [ %n, %while.body.preheader ]
    %9 = phi i32 [ %8, %while.body.preheader ], [ %13, %while.body ]
    %y.addr.0161 = bitcast i32* %y.addr.016 to <4 x i32>*
    %10 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %n.addr.014)
    %11 = tail call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %y.addr.0161, i32 4, <4 x i1> %10, <4 x i32> zeroinitializer)
    %mul = mul <4 x i32> %11, %s.015
    %add.ptr = getelementptr inbounds i32, i32* %y.addr.016, i32 4
    %12 = add i32 %n.addr.014, -4
    %13 = call i32 @llvm.loop.decrement.reg.i32(i32 %9, i32 1)
    %14 = icmp ne i32 %13, 0
    br i1 %14, label %while.body, label %while.end

  while.end:                                        ; preds = %while.body, %entry
    %s.0.lcssa = phi <4 x i32> [ <i32 1, i32 1, i32 1, i32 1>, %entry ], [ %mul, %while.body ]
    %vecext = extractelement <4 x i32> %s.0.lcssa, i32 0
    %vecext5 = extractelement <4 x i32> %s.0.lcssa, i32 1
    %add = add nsw i32 %vecext, %vecext5
    ret i32 %add
  }

  declare <4 x i1> @llvm.arm.mve.vctp32(i32) #1
  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>) #2
  declare i32 @llvm.smin.i32(i32, i32) #3
  declare i32 @llvm.start.loop.iterations.i32(i32) #4
  declare i32 @llvm.loop.decrement.reg.i32(i32, i32) #4

...
---
name:            test
tracksRegLiveness: true
liveins:
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
fixedStack:
  - { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,
      isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
  ; CHECK-LABEL: name: test
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
  ; CHECK:   liveins: $lr, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
  ; CHECK: bb.1.while.body.preheader:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r1, $r2
  ; CHECK:   $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
  ; CHECK:   tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 10, 8, implicit-def $itstate
  ; CHECK:   renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate
  ; CHECK:   renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   $lr = t2DLS killed renamable $r0
  ; CHECK: bb.2.while.body (align 4):
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.4(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r1, $r2
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4)
  ; CHECK:   renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK:   tB %bb.4, 14 /* CC::al */, $noreg
  ; CHECK: bb.3:
  ; CHECK:   successors: %bb.4(0x80000000)
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK: bb.4.while.end:
  ; CHECK:   liveins: $d0
  ; CHECK:   renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
  bb.0.entry:
    successors: %bb.1(0x50000000), %bb.3(0x30000000)
    liveins: $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    tBcc %bb.3, 11 /* CC::lt */, killed $cpsr

  bb.1.while.body.preheader:
    successors: %bb.2(0x80000000)
    liveins: $r1, $r2

    $r0 = tMOVr $r2, 14 /* CC::al */, $noreg
    tCMPi8 renamable $r2, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 10, 8, implicit-def $itstate
    renamable $r0 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r0, implicit killed $itstate
    renamable $r0, dead $cpsr = tSUBrr renamable $r2, killed renamable $r0, 14 /* CC::al */, $noreg
    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 3, 14 /* CC::al */, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $r0 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r0, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0
    renamable $lr = t2DoLoopStartTP killed renamable $r0, renamable $r2

  bb.2.while.body (align 4):
    successors: %bb.2(0x7c000000), %bb.4(0x04000000)
    liveins: $lr, $q0:0x000000000000003C, $r1, $r2

    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r1, renamable $q1 = MVE_VLDRWU32_post killed renamable $r1, 16, 1, killed renamable $vpr, $lr :: (load (s128) from %ir.y.addr.0161, align 4)
    renamable $q0 = MVE_VMULi32 killed renamable $q1, killed renamable $q0, 0, $noreg, $lr, undef renamable $q0
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopEndDec killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.4, 14 /* CC::al */, $noreg

  bb.3:
    successors: %bb.4(0x80000000)

    renamable $q0 = MVE_VMOVimmi32 1, 0, $noreg, $noreg, undef renamable $q0

  bb.4.while.end:
    liveins: $q0:0x000000000000000C

    renamable $r0, renamable $r1 = VMOVRRD killed renamable $d0, 14 /* CC::al */, $noreg
    renamable $r0 = nsw tADDhirr killed renamable $r0, killed renamable $r1, 14 /* CC::al */, $noreg
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0

...