[MLIR][Mem2Reg][LLVM] Enhance partial load support (#89094) This commit improves LLVM dialect's Mem2Reg interfaces to support promotions of partial loads from larger memory slots. To support this, the Mem2Reg interface methods are extended with additional data layout parameters. The data layout is required to determine type sizes to produce correct conversion sequences. Note: There will be additional followups that introduce a similar functionality for stores, and there are plans to support accesses into the middle of memory slots.
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