# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s

--- |
  define dso_local arm_aapcs_vfpcc void @test_wlstp8(i8* noalias nocapture %a, i8* noalias nocapture readonly %b, i8* noalias nocapture readonly %c, i32 %N) {
  entry:
    %0 = add i32 %N, 15
    %1 = lshr i32 %0, 4
    %2 = shl nuw i32 %1, 4
    %3 = add i32 %2, -16
    %4 = lshr i32 %3, 4
    %n.vec = add nuw nsw i32 %4, 1
    %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)
    br i1 %cmp, label %for.cond.cleanup, label %vector.ph

  vector.ph:                                        ; preds = %entry
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
    %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]
    %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]
    %6 = call <16 x i1> @llvm.arm.vctp8(i32 %5)
    %7 = sub i32 %5, 16
    %scevgep4 = getelementptr i8, i8* %b, i32 %index
    %scevgep45 = bitcast i8* %scevgep4 to <16 x i8>*
    %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %scevgep45, i32 1, <16 x i1> %6, <16 x i8> undef)
    %scevgep2 = getelementptr i8, i8* %c, i32 %index
    %scevgep23 = bitcast i8* %scevgep2 to <16 x i8>*
    %wide.masked.load14 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %scevgep23, i32 1, <16 x i1> %6, <16 x i8> undef)
    %tmp5 = mul <16 x i8> %wide.masked.load14, %wide.masked.load
    %scevgep = getelementptr i8, i8* %a, i32 %index
    %scevgep1 = bitcast i8* %scevgep to <16 x i8>*
    call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %tmp5, <16 x i8>* %scevgep1, i32 1, <16 x i1> %6)
    %index.next = add i32 %index, 16
    %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
    %tmp8 = icmp eq i32 %loop.dec, 0
    br i1 %tmp8, label %for.cond.cleanup, label %vector.body

  for.cond.cleanup:                                 ; preds = %vector.body, %entry
    ret void
  }

  define dso_local arm_aapcs_vfpcc void @test_wlstp16(i16* noalias nocapture %a, i16* noalias nocapture readonly %b, i16* noalias nocapture readonly %c, i32 %N) {
  entry:
    %0 = add i32 %N, 7
    %1 = lshr i32 %0, 3
    %2 = shl nuw i32 %1, 3
    %3 = add i32 %2, -8
    %4 = lshr i32 %3, 3
    %n.vec = add nuw nsw i32 %4, 1
    %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)
    br i1 %cmp, label %for.cond.cleanup, label %vector.ph

  vector.ph:                                        ; preds = %entry
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv5 = phi i16* [ %scevgep6, %vector.body ], [ %b, %vector.ph ]
    %lsr.iv2 = phi i16* [ %scevgep3, %vector.body ], [ %c, %vector.ph ]
    %lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
    %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]
    %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]
    %lsr.iv57 = bitcast i16* %lsr.iv5 to <8 x i16>*
    %lsr.iv24 = bitcast i16* %lsr.iv2 to <8 x i16>*
    %lsr.iv1 = bitcast i16* %lsr.iv to <8 x i16>*
    %6 = call <8 x i1> @llvm.arm.vctp16(i32 %5)
    %7 = sub i32 %5, 8
    %wide.masked.load = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv57, i32 2, <8 x i1> %6, <8 x i16> undef)
    %wide.masked.load14 = call <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>* %lsr.iv24, i32 2, <8 x i1> %6, <8 x i16> undef)
    %tmp5 = mul <8 x i16> %wide.masked.load14, %wide.masked.load
    call void @llvm.masked.store.v8i16.p0v8i16(<8 x i16> %tmp5, <8 x i16>* %lsr.iv1, i32 2, <8 x i1> %6)
    %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
    %tmp8 = icmp eq i32 %loop.dec, 0
    %scevgep = getelementptr i16, i16* %lsr.iv, i32 8
    %scevgep3 = getelementptr i16, i16* %lsr.iv2, i32 8
    %scevgep6 = getelementptr i16, i16* %lsr.iv5, i32 8
    br i1 %tmp8, label %for.cond.cleanup, label %vector.body

  for.cond.cleanup:                                 ; preds = %vector.body, %entry
    ret void
  }

  define dso_local i32 @test_wlstp32(i32* noalias nocapture readonly %a, i32* noalias nocapture readonly %b, i32 %N) {
  entry:
    %0 = add i32 %N, 3
    %1 = lshr i32 %0, 2
    %2 = shl nuw i32 %1, 2
    %3 = add i32 %2, -4
    %4 = lshr i32 %3, 2
    %n.vec = add nuw nsw i32 %4, 1
    %cmp = call i1 @llvm.test.set.loop.iterations.i32(i32 %n.vec)
    br i1 %cmp, label %for.cond.cleanup, label %vector.ph

  vector.ph:                                        ; preds = %entry
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv2 = phi i32* [ %scevgep3, %vector.body ], [ %a, %vector.ph ]
    %lsr.iv = phi i32* [ %scevgep, %vector.body ], [ %b, %vector.ph ]
    %count = phi i32 [ %n.vec, %vector.ph ], [ %loop.dec, %vector.body ]
    %vec.phi = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ %tmp6, %vector.body ]
    %5 = phi i32 [ %N, %vector.ph ], [ %7, %vector.body ]
    %lsr.iv24 = bitcast i32* %lsr.iv2 to <4 x i32>*
    %lsr.iv1 = bitcast i32* %lsr.iv to <4 x i32>*
    %6 = call <4 x i1> @llvm.arm.vctp32(i32 %5)
    %7 = sub i32 %5, 4
    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv24, i32 4, <4 x i1> %6, <4 x i32> undef)
    %wide.masked.load13 = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv1, i32 4, <4 x i1> %6, <4 x i32> undef)
    %tmp5 = mul nsw <4 x i32> %wide.masked.load13, %wide.masked.load
    %tmp6 = add nsw <4 x i32> %tmp5, %vec.phi
    %loop.dec = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
    %tmp7 = icmp eq i32 %loop.dec, 0
    %scevgep = getelementptr i32, i32* %lsr.iv, i32 4
    %scevgep3 = getelementptr i32, i32* %lsr.iv2, i32 4
    br i1 %tmp7, label %middle.block, label %vector.body

  middle.block:                                     ; preds = %vector.body
    %8 = call <4 x i1> @llvm.arm.vctp32(i32 %5)
    %tmp8 = select <4 x i1> %8, <4 x i32> %tmp6, <4 x i32> %vec.phi
    %tmp9 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %tmp8)
    br label %for.cond.cleanup

  for.cond.cleanup:                                 ; preds = %middle.block, %entry
    %res.0.lcssa = phi i32 [ 0, %entry ], [ %tmp9, %middle.block ]
    ret i32 %res.0.lcssa
  }

  declare i1 @llvm.test.set.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
  declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>)
  declare <8 x i16> @llvm.masked.load.v8i16.p0v8i16(<8 x i16>*, i32 immarg, <8 x i1>, <8 x i16>)
  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
  declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>)
  declare void @llvm.masked.store.v8i16.p0v8i16(<8 x i16>, <8 x i16>*, i32 immarg, <8 x i1>)
  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
  declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
  declare <16 x i1> @llvm.arm.vctp8(i32)
  declare void @llvm.stackprotector(i8*, i8**)
  declare <8 x i1> @llvm.arm.vctp16(i32)
  declare <4 x i1> @llvm.arm.vctp32(i32)
...
---
name:            test_wlstp8
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_wlstp8
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -8
  ; CHECK:   $lr = MVE_WLSTP_8 killed renamable $r3, %bb.1
  ; CHECK:   tB %bb.3, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.3(0x04000000), %bb.2(0x7c000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r12
  ; CHECK:   renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep45, align 1)
  ; CHECK:   renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 0, $noreg, $noreg :: (load (s128) from %ir.scevgep23, align 1)
  ; CHECK:   renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2ADDri killed renamable $r12, 16, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.scevgep1, align 1)
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
  bb.0.entry:
    successors: %bb.3(0x40000000), %bb.1(0x40000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $lr

    frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r4, -8
    renamable $r12 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg
    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
    renamable $r12 = t2BICri killed renamable $r12, 15, 14, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r12, 16, 14, $noreg, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 35, 14, $noreg, $noreg
    $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $r12 = t2MOVi 0, 14, $noreg, $noreg

  bb.2.vector.body:
    successors: %bb.3(0x04000000), %bb.2(0x7c000000)
    liveins: $lr, $r0, $r1, $r2, $r3, $r12

    renamable $r4 = t2ADDrr renamable $r1, renamable $r12, 14, $noreg, $noreg
    renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q0 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep45, align 1)
    renamable $r4 = t2ADDrr renamable $r2, renamable $r12, 14, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = MVE_VLDRBU8 killed renamable $r4, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.scevgep23, align 1)
    renamable $r4 = t2ADDrr renamable $r0, renamable $r12, 14, $noreg, $noreg
    renamable $r12 = t2ADDri killed renamable $r12, 16, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
    renamable $q0 = MVE_VMULi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
    MVE_VPST 8, implicit $vpr
    MVE_VSTRBU8 killed renamable $q0, killed renamable $r4, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.scevgep1, align 1)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.for.cond.cleanup:
    tPOP_RET 14, $noreg, def $r4, def $pc

...
---
name:            test_wlstp16
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_wlstp16
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   $lr = MVE_WLSTP_16 killed renamable $r3, %bb.1
  ; CHECK:   tB %bb.2, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.vector.body:
  ; CHECK:   successors: %bb.2(0x04000000), %bb.1(0x7c000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)
  ; CHECK:   renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)
  ; CHECK:   renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)
  ; CHECK:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.1
  ; CHECK: bb.2.for.cond.cleanup:
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.2(0x40000000), %bb.1(0x40000000)
    liveins: $r0, $r1, $r2, $r3, $r7, $lr

    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    renamable $r12 = t2ADDri renamable $r3, 7, 14, $noreg, $noreg
    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
    renamable $r12 = t2BICri killed renamable $r12, 7, 14, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r12, 8, 14, $noreg, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r12, 27, 14, $noreg, $noreg
    $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.2, 14, $noreg

  bb.1.vector.body:
    successors: %bb.2(0x04000000), %bb.1(0x7c000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP16 renamable $r3, 0, $noreg, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $q0 = MVE_VLDRHU16 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv57, align 2)
    renamable $q1 = MVE_VLDRHU16 renamable $r2, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 2)
    renamable $q0 = MVE_VMULi16 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
    MVE_VPST 8, implicit $vpr
    MVE_VSTRHU16 killed renamable $q0, renamable $r0, 0, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv1, align 2)
    renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
    renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 16, 14, $noreg
    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 8, 14, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.2, 14, $noreg

  bb.2.for.cond.cleanup:
    tPOP_RET 14, $noreg, def $r7, def $pc

...
---
name:            test_wlstp32
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: test_wlstp32
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.4(0x40000000), %bb.1(0x40000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   $lr = t2WLS killed renamable $lr, %bb.1
  ; CHECK:   tB %bb.4, 14 /* CC::al */, $noreg
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.3(0x04000000), %bb.2(0x7c000000)
  ; CHECK:   liveins: $lr, $q1, $r0, $r1, $r2
  ; CHECK:   $q0 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q0
  ; CHECK:   renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg
  ; CHECK:   MVE_VPST 4, implicit $vpr
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
  ; CHECK:   renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
  ; CHECK:   $r3 = tMOVr $r2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
  ; CHECK:   renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, killed renamable $vpr, $noreg, undef renamable $q1
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3.middle.block:
  ; CHECK:   successors: %bb.4(0x80000000)
  ; CHECK:   liveins: $q0, $q1, $r3
  ; CHECK:   renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg
  ; CHECK:   renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg
  ; CHECK: bb.4.for.cond.cleanup:
  ; CHECK:   liveins: $r12
  ; CHECK:   $r0 = tMOVr killed $r12, 14 /* CC::al */, $noreg
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
  bb.0.entry:
    successors: %bb.4(0x40000000), %bb.1(0x40000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    renamable $r3, dead $cpsr = tADDi3 renamable $r2, 3, 14, $noreg
    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14, $noreg, $noreg
    renamable $r12 = t2MOVi 0, 14, $noreg, $noreg
    $lr = t2WhileLoopStartLR renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.4, 14, $noreg

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $lr, $r0, $r1, $r2

    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1

  bb.2.vector.body:
    successors: %bb.3(0x04000000), %bb.2(0x7c000000)
    liveins: $lr, $q1, $r0, $r1, $r2

    $q0 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q0
    renamable $vpr = MVE_VCTP32 $r2, 0, $noreg, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv24, align 4)
    renamable $q2 = MVE_VLDRWU32 renamable $r1, 0, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv1, align 4)
    $r3 = tMOVr $r2, 14, $noreg
    renamable $q1 = nsw MVE_VMULi32 killed renamable $q2, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
    renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 16, 14, $noreg
    renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 16, 14, $noreg
    renamable $r2, dead $cpsr = tSUBi8 killed $r2, 4, 14, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = nsw MVE_VADDi32 killed renamable $q1, renamable $q0, 1, renamable $vpr, $noreg, undef renamable $q1
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14, $noreg

  bb.3.middle.block:
    successors: %bb.4(0x80000000)
    liveins: $q0, $q1, $r3

    renamable $vpr = MVE_VCTP32 killed renamable $r3, 0, $noreg, $noreg
    renamable $q0 = MVE_VPSEL killed renamable $q1, killed renamable $q0, 0, killed renamable $vpr, $noreg
    renamable $r12 = MVE_VADDVu32no_acc killed renamable $q0, 0, $noreg, $noreg

  bb.4.for.cond.cleanup:
    liveins: $r12

    $r0 = tMOVr killed $r12, 14, $noreg
    tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0

...