# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s

--- |
  @_ZL3arr = internal global [10 x i32] [i32 1, i32 2, i32 3, i32 5, i32 5, i32 5, i32 -2, i32 0, i32 -8, i32 -1], align 4
  @.str = private unnamed_addr constant [5 x i8] c"%d, \00", align 1

  define arm_aapcs_vfpcc void @vpt_block(i32* nocapture %A, i32 %n, i32 %x) {
  entry:
    %cmp9 = icmp sgt i32 %n, 0
    %0 = add i32 %n, 3
    %1 = lshr i32 %0, 2
    %2 = shl nuw i32 %1, 2
    %3 = add i32 %2, -4
    %4 = lshr i32 %3, 2
    %5 = add nuw nsw i32 %4, 1
    br i1 %cmp9, label %vector.ph, label %for.cond.cleanup

  vector.ph:                                        ; preds = %entry
    %sub = sub nsw i32 0, %x
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %A, %vector.ph ]
    %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ]
    %7 = phi i32 [ %n, %vector.ph ], [ %9, %vector.body ]
    %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>*
    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
    %9 = sub i32 %7, 4
    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)
    %10 = insertelement <4 x i32> undef, i32 %x, i32 0
    %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer
    %12 = icmp slt <4 x i32> %wide.masked.load, %11
    %13 = insertelement <4 x i32> undef, i32 %sub, i32 0
    %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer
    %15 = icmp sgt <4 x i32> %wide.masked.load, %14
    %16 = and <4 x i1> %12, %15
    %17 = and <4 x i1> %16, %8
    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17)
    %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4
    %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
    %19 = icmp ne i32 %18, 0
    br i1 %19, label %vector.body, label %for.cond.cleanup

  for.cond.cleanup:                                 ; preds = %vector.body, %entry
    ret void
  }

  define arm_aapcs_vfpcc void @different_vcpt_reaching_def(i32* nocapture %A, i32 %n, i32 %x) {
    ; Intentionally left blank - see MIR sequence below.
    entry:
      unreachable
    vector.ph:
      unreachable
    vector.body:
      unreachable
    for.cond.cleanup:
      unreachable
  }

  define arm_aapcs_vfpcc void @different_vcpt_operand(i32* nocapture %A, i32 %n, i32 %x) {
    ; Intentionally left blank - see MIR sequence below.
    entry:
      unreachable
    vector.ph:
      unreachable
    vector.body:
      unreachable
    for.cond.cleanup:
      unreachable
  }

  define arm_aapcs_vfpcc void @else_vcpt(i32* nocapture %data, i32 %N, i32 %T) {
  entry:
    %cmp9 = icmp sgt i32 %N, 0
    %0 = add i32 %N, 3
    %1 = lshr i32 %0, 2
    %2 = shl nuw i32 %1, 2
    %3 = add i32 %2, -4
    %4 = lshr i32 %3, 2
    %5 = add nuw nsw i32 %4, 1
    br i1 %cmp9, label %vector.ph, label %for.cond.cleanup

  vector.ph:                                        ; preds = %entry
    %sub = sub nsw i32 0, %T
    %start = call i32 @llvm.start.loop.iterations.i32(i32 %5)
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv1 = phi i32* [ %scevgep, %vector.body ], [ %data, %vector.ph ]
    %6 = phi i32 [ %start, %vector.ph ], [ %18, %vector.body ]
    %7 = phi i32 [ %N, %vector.ph ], [ %9, %vector.body ]
    %lsr.iv12 = bitcast i32* %lsr.iv1 to <4 x i32>*
    %8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %7)
    %9 = sub i32 %7, 4
    %wide.masked.load = call <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>* %lsr.iv12, i32 4, <4 x i1> %8, <4 x i32> undef)
    %10 = insertelement <4 x i32> undef, i32 %T, i32 0
    %11 = shufflevector <4 x i32> %10, <4 x i32> undef, <4 x i32> zeroinitializer
    %12 = icmp slt <4 x i32> %wide.masked.load, %11
    %13 = insertelement <4 x i32> undef, i32 %sub, i32 0
    %14 = shufflevector <4 x i32> %13, <4 x i32> undef, <4 x i32> zeroinitializer
    %15 = icmp sgt <4 x i32> %wide.masked.load, %14
    %16 = or <4 x i1> %12, %15
    %17 = and <4 x i1> %16, %8
    call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> zeroinitializer, <4 x i32>* %lsr.iv12, i32 4, <4 x i1> %17)
    %scevgep = getelementptr i32, i32* %lsr.iv1, i32 4
    %18 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %6, i32 1)
    %19 = icmp ne i32 %18, 0
    br i1 %19, label %vector.body, label %for.cond.cleanup

  for.cond.cleanup:                                 ; preds = %vector.body, %entry
    ret void
  }

  define arm_aapcs_vfpcc void @loop_invariant_vpt_operands(i32* nocapture %A, i32 %n, i32 %x) {
    ; Intentionally left blank - see MIR sequence below.
    entry:
      unreachable
    vector.ph:
      unreachable
    vector.body:
      unreachable
    for.cond.cleanup:
      unreachable
  }

  define arm_aapcs_vfpcc void @vctp_before_vpt(i32* nocapture %A, i32 %n, i32 %x) {
    ; Intentionally left blank - see MIR sequence below.
    entry:
      unreachable
    vector.ph:
      unreachable
    vector.body:
      unreachable
    for.cond.cleanup:
      unreachable
  }

  define arm_aapcs_vfpcc void @vpt_load_vctp_store(i32* nocapture %A, i32 %n, i32 %x) {
    ; Intentionally left blank - see MIR sequence below.
    entry:
      unreachable
    vector.ph:
      unreachable
    vector.body:
      unreachable
    for.cond.cleanup:
      unreachable
  }

  define arm_aapcs_vfpcc void @emptyblock() {
    unreachable
  }
  define arm_aapcs_vfpcc void @predvcmp() {
    unreachable
  }
  define arm_aapcs_vfpcc void @predvpt() {
    unreachable
  }

  declare <4 x i32> @llvm.masked.load.v4i32.p0v4i32(<4 x i32>*, i32 immarg, <4 x i1>, <4 x i32>)
  declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32 immarg, <4 x i1>)
  declare i32 @llvm.start.loop.iterations.i32(i32)
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
  declare <4 x i1> @llvm.arm.mve.vctp32(i32)
...
---
name:            vpt_block
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: vpt_block
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r1
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r2, $r3
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
  ; CHECK:   MVE_VPTv4s32r 4, renamable $q1, renamable $r2, 11, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
    MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            different_vcpt_reaching_def
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: different_vcpt_reaching_def
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
  ; CHECK:   MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ;
  ; Tests that secondary VCTPs are refused when their operand's reaching definition is not the same as the main
  ; VCTP's.
  ;
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, renamable $vpr, $noreg
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
    MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            different_vcpt_operand
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: different_vcpt_operand
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2, $r3
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
  ; CHECK:   MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ;
  ; Tests that secondary VCTPs are refused when their operand is not the same register as the main VCTP's.
  ;
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
    MVE_VPTv4s32r 2, renamable $q1, renamable $r2, 11, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            else_vcpt
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: else_vcpt
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r1
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r2, $r3
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
  ; CHECK:   MVE_VPTv4s32r 12, renamable $q1, renamable $r2, 10, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ;
  ; Test including a else-predicated VCTP.
  ;
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
    MVE_VPTv4s32r 14, renamable $q1, renamable $r2, 10, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 13, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 2, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 2, killed renamable $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            loop_invariant_vpt_operands
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: loop_invariant_vpt_operands
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r1
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r2, $r3
  ; CHECK:   renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 0, killed $noreg, $noreg
  ; CHECK:   MVE_VPTv4s32r 4, renamable $q0, renamable $r2, 11, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr
    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $q1 = MVE_VLDRWU32 renamable $r0, 0, 1, killed renamable $vpr, $noreg
    MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 11, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q1, renamable $r3, 12, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            vctp_before_vpt
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: vctp_before_vpt
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r1, $r2
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r1
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r2, $r3
  ; CHECK:   MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
  ; CHECK:   dead renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr
    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    MVE_VPTv4s32r 8, renamable $q0, renamable $r2, 8, implicit-def $vpr
    renamable $vpr = MVE_VCMPs32r killed renamable $q0, renamable $r3, 12, 1, killed renamable $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            vpt_load_vctp_store
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       8
  offsetAdjustment: 0
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: vpt_load_vctp_store
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1.vector.ph:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   dead renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK: bb.2.vector.body:
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r0, $r1, $r2
  ; CHECK:   MVE_VPTv4s32r 2, killed renamable $q0, renamable $r2, 2, implicit-def $vpr
  ; CHECK:   renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r1, 1, killed $vpr, $noreg
  ; CHECK:   MVE_VSTRWU32 renamable $q0, renamable $r0, 0, 1, killed $vpr, $noreg
  ; CHECK:   renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3.for.cond.cleanup:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ;
  ; This shouldn't be tail-predicated because the VLDR isn't predicated on the VCTP.
  ;
  bb.0.entry:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr
    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r1, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1.vector.ph:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    renamable $r3, dead $cpsr = tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = nsw tRSB renamable $r2, 14 /* CC::al */, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.2.vector.body:
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1, $r2, $r3

    MVE_VPTv4s32r 2, renamable $q0, renamable $r2, 2, implicit-def $vpr
    renamable $q0 = MVE_VLDRWU32 renamable $r0, 0, 1, $vpr, $noreg
    renamable $vpr = MVE_VCTP32 renamable $r1, 1, $vpr, $noreg
    MVE_VSTRWU32 killed renamable $q0, killed renamable $r0, 0, 1, $vpr, $noreg
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3.for.cond.cleanup:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
...
---
name:            emptyblock
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
  ; CHECK-LABEL: name: emptyblock
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x50000000), %bb.3(0x30000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 12
  ; CHECK:   tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.3, 11 /* CC::lt */, killed $cpsr
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
  ; CHECK:   renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
  ; CHECK:   VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r0
  ; CHECK: bb.2 (align 4):
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $r1
  ; CHECK:   renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3:
  ; CHECK:   $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
  bb.0:
    successors: %bb.1(0x50000000), %bb.3(0x30000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    $sp = frame-setup tSUBspi $sp, 1, 14 /* CC::al */, $noreg
    frame-setup CFI_INSTRUCTION def_cfa_offset 12
    tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    tBcc %bb.3, 11 /* CC::lt */, killed $cpsr

  bb.1:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2

    tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
    renamable $r2 = t2CSINC $zr, $zr, 0, implicit killed $cpsr
    renamable $r3, dead $cpsr = tADDi3 renamable $r0, 3, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q0
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $r12 = t2ANDri killed renamable $r2, 1, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
    renamable $r2, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r2, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $r2 = t2RSBri killed renamable $r12, 0, 14 /* CC::al */, $noreg, $noreg
    $vpr = VMSR_P0 killed $r2, 14 /* CC::al */, $noreg
    VSTR_P0_off killed renamable $vpr, $sp, 0, 14 /* CC::al */, $noreg :: (store (s32) into %stack.0)
    renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r0

  bb.2 (align 4):
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $r0, $r1

    renamable $vpr = VLDR_P0_off $sp, 0, 14 /* CC::al */, $noreg :: (load (s32) from %stack.0)
    MVE_VPST 8, implicit $vpr
    renamable $vpr = MVE_VCTP32 renamable $r0, 1, killed renamable $vpr, $noreg
    renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r1 = MVE_VSTRWU32_post renamable $q0, killed renamable $r1, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3:
    $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit undef $r0
...
---
name:            predvcmp
alignment:       8
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
  - id:              0
    value:           '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
    alignment:       8
    isTargetSpecific: false
body:             |
  ; CHECK-LABEL: name: predvcmp
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
  ; CHECK:   renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
  ; CHECK:   $lr = MVE_DLSTP_32 killed renamable $r2
  ; CHECK: bb.2 (align 4):
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $q1, $q2, $r0, $r1
  ; CHECK:   MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.2
  ; CHECK: bb.3:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ; CHECK: bb.4 (align 8):
  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2

    renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
    renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
    renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
    renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2

  bb.2 (align 4):
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2

    renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $vpr = MVE_VCMPs32r renamable $q0, renamable $r1, 11, 1, killed renamable $vpr, $noreg
    renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
    renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc

  bb.4 (align 8):
    CONSTPOOL_ENTRY 0, %const.0, 16

...
---
name:            predvpt
alignment:       8
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
constants:
  - id:              0
    value:           '<4 x i32> <i32 0, i32 1, i32 2, i32 3>'
    alignment:       8
    isTargetSpecific: false
body:             |
  ; CHECK-LABEL: name: predvpt
  ; CHECK: bb.0:
  ; CHECK:   successors: %bb.1(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r7
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   t2IT 11, 8, implicit-def $itstate
  ; CHECK:   frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate
  ; CHECK: bb.1:
  ; CHECK:   successors: %bb.2(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2
  ; CHECK:   renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
  ; CHECK:   renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
  ; CHECK:   renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
  ; CHECK: bb.2 (align 4):
  ; CHECK:   successors: %bb.2(0x7c000000), %bb.3(0x04000000)
  ; CHECK:   liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2
  ; CHECK:   MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
  ; CHECK:   renamable $vpr = MVE_VCTP32 renamable $r2, 1, killed $vpr, $noreg
  ; CHECK:   MVE_VPST 8, implicit $vpr
  ; CHECK:   renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
  ; CHECK:   renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.2
  ; CHECK: bb.3:
  ; CHECK:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
  ; CHECK: bb.4 (align 8):
  ; CHECK:   CONSTPOOL_ENTRY 0, %const.0, 16
  bb.0:
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r2, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    tCMPi8 renamable $r2, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
    t2IT 11, 8, implicit-def $itstate
    frame-destroy tPOP_RET 11 /* CC::lt */, killed $cpsr, def $r7, def $pc, implicit killed $itstate

  bb.1:
    successors: %bb.2(0x80000000)
    liveins: $r0, $r1, $r2

    renamable $r12 = t2LEApcrel %const.0, 14 /* CC::al */, $noreg
    renamable $r3, dead $cpsr = nuw tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
    renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
    renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, $noreg, undef renamable $q1
    renamable $q0 = MVE_VLDRWU32 killed renamable $r12, 0, 0, $noreg, $noreg :: (load (s128) from constant-pool, align 8)
    renamable $r12 = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r12, 19, 14 /* CC::al */, $noreg, $noreg
    renamable $q2 = MVE_VMOVimmi32 4, 0, $noreg, $noreg, undef renamable $q2
    renamable $lr = t2DoLoopStartTP killed renamable $lr, renamable $r2

  bb.2 (align 4):
    successors: %bb.2(0x7c000000), %bb.3(0x04000000)
    liveins: $lr, $q0, $q1, $q2, $r0, $r1, $r2

    MVE_VPTv4s32r 8, renamable $q0, renamable $r1, 11, implicit-def $vpr
    renamable $vpr = MVE_VCTP32 renamable $r2, 1, $vpr, $noreg
    MVE_VPST 8, implicit $vpr
    renamable $r0 = MVE_VSTRWU32_post renamable $q1, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128), align 4)
    renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VADDi32 killed renamable $q0, renamable $q2, 0, $noreg, $noreg, undef renamable $q0
    renamable $lr = t2LoopDec killed renamable $lr, 1, implicit-def dead $cpsr
    t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
    tB %bb.3, 14 /* CC::al */, $noreg

  bb.3:
    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc

  bb.4 (align 8):
    CONSTPOOL_ENTRY 0, %const.0, 16
...