llvm/test/CodeGen/ARM/GlobalISel/thumb-select-shifts.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @test_ashr_rr() { ret void }

  define void @test_shl_ri() { ret void }
  define void @test_shl_ri_bad_imm() { ret void }
...
---
name:            test_ashr_rr
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_ashr_rr
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2ASRrr:%[0-9]+]]:rgpr = t2ASRrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2ASRrr]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = G_ASHR %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_shl_ri
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_shl_ri
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[t2LSLri:%[0-9]+]]:rgpr = t2LSLri [[COPY]], 31, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2LSLri]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 31
    %2(s32) = G_SHL %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_shl_ri_bad_imm
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_shl_ri_bad_imm
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 32, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: [[t2LSLrr:%[0-9]+]]:rgpr = t2LSLrr [[COPY]], [[t2MOVi]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2LSLrr]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 32

    %2(s32) = G_SHL %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...