llvm/test/CodeGen/ARM/GlobalISel/thumb-select-load-store.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @test_s8() { ret void }
  define void @test_s16() { ret void }
  define void @test_s32() { ret void }

  define void @test_gep() { ret void }

  define void @test_load_from_stack() { ret void }
...
---
name:            test_s8
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_s8
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
    ; CHECK: [[t2LDRBi12_:%[0-9]+]]:rgpr = t2LDRBi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s8))
    ; CHECK: t2STRBi12 [[t2LDRBi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s8))
    ; CHECK: BX_RET 14 /* CC::al */, $noreg
    %0(p0) = COPY $r0

    %1(s8) = G_LOAD %0(p0) :: (load (s8))

    G_STORE %1(s8), %0(p0) :: (store (s8))

    BX_RET 14, $noreg
...
---
name:            test_s16
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_s16
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
    ; CHECK: [[t2LDRHi12_:%[0-9]+]]:rgpr = t2LDRHi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s16))
    ; CHECK: t2STRHi12 [[t2LDRHi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s16))
    ; CHECK: BX_RET 14 /* CC::al */, $noreg
    %0(p0) = COPY $r0

    %1(s16) = G_LOAD %0(p0) :: (load (s16))

    G_STORE %1(s16), %0(p0) :: (store (s16))

    BX_RET 14, $noreg
...
---
name:            test_s32
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_s32
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
    ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[COPY]], 0, 14 /* CC::al */, $noreg :: (load (s32))
    ; CHECK: t2STRi12 [[t2LDRi12_]], [[COPY]], 0, 14 /* CC::al */, $noreg :: (store (s32))
    ; CHECK: BX_RET 14 /* CC::al */, $noreg
    %0(p0) = COPY $r0

    %1(s32) = G_LOAD %0(p0) :: (load (s32))

    G_STORE %1(s32), %0(p0) :: (store (s32))

    BX_RET 14, $noreg
...
---
name:            test_gep
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_gep
    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2ADDrr]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(p0) = COPY $r0

    %1(s32) = COPY $r1

    %2(p0) = G_PTR_ADD %0, %1(s32)

    $r0 = COPY %2(p0)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_load_from_stack
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
  - { id: 4, class: gprb }
fixedStack:
  - { id: 0, offset: 0, size: 1, alignment: 4, isImmutable: true, isAliased: false }
  - { id: 1, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
  - { id: 2, offset: 8, size: 4, alignment: 4, isImmutable: true, isAliased: false }
body:             |
  bb.0:
    liveins: $r0, $r1, $r2, $r3

    ; CHECK-LABEL: name: test_load_from_stack
    ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.0, 0, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 [[t2ADDri]], 0, 14 /* CC::al */, $noreg :: (load (s32))
    ; CHECK: $r0 = COPY [[t2LDRi12_]]
    ; CHECK: [[t2ADDri1:%[0-9]+]]:rgpr = t2ADDri %fixed-stack.2, 0, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: [[t2LDRBi12_:%[0-9]+]]:gprnopc = t2LDRBi12 [[t2ADDri1]], 0, 14 /* CC::al */, $noreg :: (load (s8))
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY [[t2LDRBi12_]]
    ; CHECK: $r0 = COPY [[COPY]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg
    %0(p0) = G_FRAME_INDEX %fixed-stack.2

    %1(s32) = G_LOAD %0(p0) :: (load (s32))

    $r0 = COPY %1

    %2(p0) = G_FRAME_INDEX %fixed-stack.0

    %3(s8) = G_LOAD %2(p0) :: (load (s8))

    %4(s32) = G_ANYEXT %3(s8)

    $r0 = COPY %4

    BX_RET 14, $noreg
...