llvm/test/CodeGen/ARM/GlobalISel/thumb-select-arithmetic-ops.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple thumb-- -mattr=+v6t2,+hwdiv -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
--- |
  define void @test_add_regs() { ret void }
  define void @test_add_fold_imm() { ret void }
  define void @test_add_fold_imm12() { ret void }
  define void @test_add_no_fold_imm() { ret void }

  define void @test_sub_imm_lhs() { ret void }
  define void @test_sub_imm_rhs() { ret void }

  define void @test_mul() { ret void }
  define void @test_mla() { ret void }

  define void @test_sdiv() { ret void }
  define void @test_udiv() { ret void }
...
---
name:            test_add_regs
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_add_regs
    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2ADDrr]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = G_ADD %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_add_fold_imm
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_add_fold_imm
    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
    ; CHECK: [[t2ADDri:%[0-9]+]]:rgpr = t2ADDri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2ADDri]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
    %2(s32) = G_ADD %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_add_fold_imm12
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_add_fold_imm12
    ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0
    ; CHECK: [[t2ADDri12_:%[0-9]+]]:rgpr = t2ADDri12 [[COPY]], 4093, 14 /* CC::al */, $noreg
    ; CHECK: $r0 = COPY [[t2ADDri12_]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 4093
    %2(s32) = G_ADD %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_add_no_fold_imm
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_add_no_fold_imm
    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
    ; CHECK: [[t2MOVi32imm:%[0-9]+]]:rgpr = t2MOVi32imm 185470479
    ; CHECK: [[t2ADDrr:%[0-9]+]]:gprnopc = t2ADDrr [[COPY]], [[t2MOVi32imm]], 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2ADDrr]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 185470479 ; 0x0b0e0e0f

    %2(s32) = G_ADD %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_sub_imm_lhs
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_sub_imm_lhs
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[t2RSBri:%[0-9]+]]:rgpr = t2RSBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2RSBri]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
    %2(s32) = G_SUB %1, %0

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_sub_imm_rhs
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0

    ; CHECK-LABEL: name: test_sub_imm_rhs
    ; CHECK: [[COPY:%[0-9]+]]:gprnopc = COPY $r0
    ; CHECK: [[t2SUBri:%[0-9]+]]:rgpr = t2SUBri [[COPY]], 786444, 14 /* CC::al */, $noreg, $noreg
    ; CHECK: $r0 = COPY [[t2SUBri]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = G_CONSTANT i32 786444 ; 0x000c000c
    %2(s32) = G_SUB %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_mul
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_mul
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2MUL:%[0-9]+]]:rgpr = t2MUL [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
    ; CHECK: $r0 = COPY [[t2MUL]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = G_MUL %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_mla
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
  - { id: 3, class: gprb }
  - { id: 4, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1, $r2

    ; CHECK-LABEL: name: test_mla
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[COPY2:%[0-9]+]]:rgpr = COPY $r2
    ; CHECK: [[t2MLA:%[0-9]+]]:rgpr = t2MLA [[COPY]], [[COPY1]], [[COPY2]], 14 /* CC::al */, $noreg
    ; CHECK: $r0 = COPY [[t2MLA]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = COPY $r2

    %3(s32) = G_MUL %0, %1
    %4(s32) = G_ADD %3, %2

    $r0 = COPY %4(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_sdiv
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_sdiv
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2SDIV:%[0-9]+]]:rgpr = t2SDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
    ; CHECK: $r0 = COPY [[t2SDIV]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = G_SDIV %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...
---
name:            test_udiv
legalized:       true
regBankSelected: true
selected:        false
registers:
  - { id: 0, class: gprb }
  - { id: 1, class: gprb }
  - { id: 2, class: gprb }
body:             |
  bb.0:
    liveins: $r0, $r1

    ; CHECK-LABEL: name: test_udiv
    ; CHECK: [[COPY:%[0-9]+]]:rgpr = COPY $r0
    ; CHECK: [[COPY1:%[0-9]+]]:rgpr = COPY $r1
    ; CHECK: [[t2UDIV:%[0-9]+]]:rgpr = t2UDIV [[COPY]], [[COPY1]], 14 /* CC::al */, $noreg
    ; CHECK: $r0 = COPY [[t2UDIV]]
    ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    %0(s32) = COPY $r0

    %1(s32) = COPY $r1

    %2(s32) = G_UDIV %0, %1

    $r0 = COPY %2(s32)

    BX_RET 14, $noreg, implicit $r0
...