)]}'
{
  "commit": "a7c85052ebe7813da50cd461fdccccacb296017a",
  "tree": "1db9c04e8f7262bcafe141d01c48ed25cc0ed005",
  "parents": [
    "8bfca268ba57dcfc977a7f1d4cc6f563bb9be67a"
  ],
  "author": {
    "name": "Kirill Vedernikov",
    "email": "kvedernikov@nvidia.com",
    "time": "Fri Nov 28 11:03:32 2025 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Nov 28 15:33:32 2025 +0530"
  },
  "message": "[MLIR] Supported sparse MMA intrinsics in the MLIR-\u003eNVVM IR-\u003eNVPTX flow (#168686)\n\nThis change adds sparse MMA intrinsics to the MLIR -\u003e NVVM IR -\u003e NVPTX\nflow. NVVM and NVPTX implementation is based on PTX ISA 9.0.",
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