[AArch64][llvm] Fix disassembly of `ldt{add,set,clr}` instructions using `xzr/wzr` (#152292)

The current disassembly of `ldt{add,set,clr}` instructions when using
`xzr/wzr` is incorrect. The Armv9.6-A Memory Systems specification says:

```
  For each of LDT{ADD|SET|CLR}{L}, there is the corresponding STT{ADD|SET|CLR}{L}
  alias, for the case where the register selected by the Rt field is XZR or WZR
```
and:
```
  LDT{ADD|SET|CLR}{A}{L} is equivalent to LD{ADD|SET|CLR}{A}{L} except that: <..conditions..>
```

The Arm ARM specifies the preferred form of disassembly for these
aliases:
```
   STADD <Xs>, [<Xn|SP>]
   is equivalent to
   LDADD <Xs>, XZR, [<Xn|SP>]
   and is always the preferred disassembly.
```
(ref: DDI 0487L.b C6-2317)

This means that `sttadd` is the preferred disassembly for `ldtadd w0,
wzr, [x2]` when Rt is `xzr` or `wzr`.

This change also aligns llvm disassembly with GNU binutils, as shown by
the following examples:

llvm before this change:
```
% cat test.s
stadd w0, [sp]
sttadd w0, [sp]
ldadd w0, wzr, [sp]
ldtadd w0, wzr, [sp]

% llvm-mc-20 -triple aarch64 -mattr=+lse,+lsui test.s
        stadd   w0, [sp]
        ldtadd  w0, wzr, [sp]
        stadd   w0, [sp]
        ldtadd  w0, wzr, [sp]
```
llvm after this change:
```
% llvm-mc -triple aarch64 -mattr=+lse,+lsui test.s
        stadd   w0, [sp]
        sttadd  w0, [sp]
        stadd   w0, [sp]
        sttadd  w0, [sp]
```
GCC-15 test:
```
% gas test.s -march=armv8-a+lsui+lse -o test.o
% objdump -dr test.o
   0:   b82003ff        stadd   w0, [sp]
   4:   192007ff        sttadd  w0, [sp]
   8:   b82003ff        stadd   w0, [sp]
   c:   192007ff        sttadd  w0, [sp]
```
Many thanks to Ezra Sitorus and Alice Carlotti for reporting and
confirming this issue.