)]}'
{
  "commit": "a4d6fe54a7c3c967d88862e51660a5cdabc080bb",
  "tree": "702fa1aeb08090f00799ab1f6db34f51704aa7b0",
  "parents": [
    "dc84337f7b5bb2447e30f3364ebc863e9e04b8be"
  ],
  "author": {
    "name": "Jack Styles",
    "email": "jack.styles@arm.com",
    "time": "Tue Oct 22 08:18:09 2024 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Oct 22 08:18:09 2024 +0100"
  },
  "message": "Reland \"[llvm][ARM] Add Addend Checks for MOVT and MOVW instructions. (PR #111970)\" (#112877)\n\n**Change relanded after feedback on failures and improvements to the\r\ncheck of the addend. Original PR #111970**\r\nChanges from original patch:\r\n- The value that is being checked has changed, it is now correctly\r\nchecking any Addend for the instruction, rather than the Value. The\r\naddend is kept within the Target data structure from my investigation.\r\n- Removed changes to the following tests due to the original behaviour\r\nbeing correct, and my original patch causing unexpected errors\r\n    - llvm/test/MC/ARM/Windows/mov32t-range.s\r\n    - llvm/test/MC/MachO/ARM/thumb2-movw-fixup.s\r\n\r\nAs per the ARM ABI, the MOVT and MOVW instructions should have addends\r\nthat fall within a 16bit signed range. LLVM does not check this so it is\r\npossible to use addends that are beyond the accepted range. These\r\naddends are silently truncated.\r\n\r\nA new check is added to ensure the addend falls within the expected\r\nrange, rejecting an addend that falls outside with an error.\r\n\r\nInformation relating to the ABI requirements can be found here:\r\nhttps://github.com/ARM-software/abi-aa/blob/main/aaelf32/aaelf32.rst#addends-and-pc-bias-compensation",
  "tree_diff": [
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