)]}'
{
  "commit": "a1f369e6309c8c6adaae886afc55817b97953641",
  "tree": "a6c898776a2b1b43627dfe5ed58ac93bf3d904ef",
  "parents": [
    "1ce709cb845b8b0bc4625198afa7a26c0a198fe4"
  ],
  "author": {
    "name": "Nicholas Guy",
    "email": "nicholas.guy@arm.com",
    "time": "Wed Apr 23 13:19:41 2025 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Apr 23 13:19:41 2025 +0100"
  },
  "message": "[AArch64][SVE] Add dot product lowering for PARTIAL_REDUCE_MLA node (#130933)\n\nAdd lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only\nhappens when the combine has been performed on the ISD node. Also adds\nin check to only do the DAG combine when the node can then eventually be\nlowered, so changes neon tests too.\n\n---------\n\nCo-authored-by: James Chesterman \u003cjames.chesterman@arm.com\u003e",
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