tree dafc4bfc9c2d013dd0bb5bc5b9cae73be9351954
parent 7e9351b9dee225b9ab12ee9bbfc9f8b96ddd1a1d
author Malhar Jajoo <malhar.jajoo@arm.com> 1620261500 +0100
committer Malhar Jajoo <malhar.jajoo@arm.com> 1620339688 +0100

[ARM] Transforming memcpy to Tail predicated Loop

This patch converts llvm.memcpy intrinsic into Tail Predicated
Hardware loops for a target that supports the Arm M-profile
Vector Extension (MVE).

From an implementation point of view, the patch

- adds an ARM specific SDAG Node (to which the llvm.memcpy intrinsic is lowered to, during first phase of ISel)
- adds a corresponding TableGen entry to generate a pseudo instruction, with a custom inserter,
  on matching the above node.
- Adds a custom inserter function that expands the pseudo instruction into MIR suitable
   to be (by later passes) into a WLSTP loop.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99723