| //===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "AMDKernelCodeT.h" |
| #include "MCTargetDesc/AMDGPUMCTargetDesc.h" |
| #include "MCTargetDesc/AMDGPUTargetStreamer.h" |
| #include "SIDefines.h" |
| #include "SIInstrInfo.h" |
| #include "SIRegisterInfo.h" |
| #include "TargetInfo/AMDGPUTargetInfo.h" |
| #include "Utils/AMDGPUAsmUtils.h" |
| #include "Utils/AMDGPUBaseInfo.h" |
| #include "Utils/AMDKernelCodeTUtils.h" |
| #include "llvm/ADT/APFloat.h" |
| #include "llvm/ADT/SmallBitVector.h" |
| #include "llvm/ADT/StringSet.h" |
| #include "llvm/ADT/Twine.h" |
| #include "llvm/MC/MCAsmInfo.h" |
| #include "llvm/MC/MCContext.h" |
| #include "llvm/MC/MCExpr.h" |
| #include "llvm/MC/MCInst.h" |
| #include "llvm/MC/MCParser/MCAsmParser.h" |
| #include "llvm/MC/MCParser/MCParsedAsmOperand.h" |
| #include "llvm/MC/MCParser/MCTargetAsmParser.h" |
| #include "llvm/MC/MCSymbol.h" |
| #include "llvm/MC/TargetRegistry.h" |
| #include "llvm/Support/AMDGPUMetadata.h" |
| #include "llvm/Support/AMDHSAKernelDescriptor.h" |
| #include "llvm/Support/Casting.h" |
| #include "llvm/Support/MachineValueType.h" |
| #include "llvm/Support/TargetParser.h" |
| |
| using namespace llvm; |
| using namespace llvm::AMDGPU; |
| using namespace llvm::amdhsa; |
| |
| namespace { |
| |
| class AMDGPUAsmParser; |
| |
| enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL }; |
| |
| //===----------------------------------------------------------------------===// |
| // Operand |
| //===----------------------------------------------------------------------===// |
| |
| class AMDGPUOperand : public MCParsedAsmOperand { |
| enum KindTy { |
| Token, |
| Immediate, |
| Register, |
| Expression |
| } Kind; |
| |
| SMLoc StartLoc, EndLoc; |
| const AMDGPUAsmParser *AsmParser; |
| |
| public: |
| AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_) |
| : MCParsedAsmOperand(), Kind(Kind_), AsmParser(AsmParser_) {} |
| |
| using Ptr = std::unique_ptr<AMDGPUOperand>; |
| |
| struct Modifiers { |
| bool Abs = false; |
| bool Neg = false; |
| bool Sext = false; |
| |
| bool hasFPModifiers() const { return Abs || Neg; } |
| bool hasIntModifiers() const { return Sext; } |
| bool hasModifiers() const { return hasFPModifiers() || hasIntModifiers(); } |
| |
| int64_t getFPModifiersOperand() const { |
| int64_t Operand = 0; |
| Operand |= Abs ? SISrcMods::ABS : 0u; |
| Operand |= Neg ? SISrcMods::NEG : 0u; |
| return Operand; |
| } |
| |
| int64_t getIntModifiersOperand() const { |
| int64_t Operand = 0; |
| Operand |= Sext ? SISrcMods::SEXT : 0u; |
| return Operand; |
| } |
| |
| int64_t getModifiersOperand() const { |
| assert(!(hasFPModifiers() && hasIntModifiers()) |
| && "fp and int modifiers should not be used simultaneously"); |
| if (hasFPModifiers()) { |
| return getFPModifiersOperand(); |
| } else if (hasIntModifiers()) { |
| return getIntModifiersOperand(); |
| } else { |
| return 0; |
| } |
| } |
| |
| friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods); |
| }; |
| |
| enum ImmTy { |
| ImmTyNone, |
| ImmTyGDS, |
| ImmTyLDS, |
| ImmTyOffen, |
| ImmTyIdxen, |
| ImmTyAddr64, |
| ImmTyOffset, |
| ImmTyInstOffset, |
| ImmTyOffset0, |
| ImmTyOffset1, |
| ImmTyCPol, |
| ImmTySWZ, |
| ImmTyTFE, |
| ImmTyD16, |
| ImmTyClampSI, |
| ImmTyOModSI, |
| ImmTyDPP8, |
| ImmTyDppCtrl, |
| ImmTyDppRowMask, |
| ImmTyDppBankMask, |
| ImmTyDppBoundCtrl, |
| ImmTyDppFi, |
| ImmTySdwaDstSel, |
| ImmTySdwaSrc0Sel, |
| ImmTySdwaSrc1Sel, |
| ImmTySdwaDstUnused, |
| ImmTyDMask, |
| ImmTyDim, |
| ImmTyUNorm, |
| ImmTyDA, |
| ImmTyR128A16, |
| ImmTyA16, |
| ImmTyLWE, |
| ImmTyExpTgt, |
| ImmTyExpCompr, |
| ImmTyExpVM, |
| ImmTyFORMAT, |
| ImmTyHwreg, |
| ImmTyOff, |
| ImmTySendMsg, |
| ImmTyInterpSlot, |
| ImmTyInterpAttr, |
| ImmTyAttrChan, |
| ImmTyOpSel, |
| ImmTyOpSelHi, |
| ImmTyNegLo, |
| ImmTyNegHi, |
| ImmTySwizzle, |
| ImmTyGprIdxMode, |
| ImmTyHigh, |
| ImmTyBLGP, |
| ImmTyCBSZ, |
| ImmTyABID, |
| ImmTyEndpgm, |
| }; |
| |
| enum ImmKindTy { |
| ImmKindTyNone, |
| ImmKindTyLiteral, |
| ImmKindTyConst, |
| }; |
| |
| private: |
| struct TokOp { |
| const char *Data; |
| unsigned Length; |
| }; |
| |
| struct ImmOp { |
| int64_t Val; |
| ImmTy Type; |
| bool IsFPImm; |
| mutable ImmKindTy Kind; |
| Modifiers Mods; |
| }; |
| |
| struct RegOp { |
| unsigned RegNo; |
| Modifiers Mods; |
| }; |
| |
| union { |
| TokOp Tok; |
| ImmOp Imm; |
| RegOp Reg; |
| const MCExpr *Expr; |
| }; |
| |
| public: |
| bool isToken() const override { |
| if (Kind == Token) |
| return true; |
| |
| // When parsing operands, we can't always tell if something was meant to be |
| // a token, like 'gds', or an expression that references a global variable. |
| // In this case, we assume the string is an expression, and if we need to |
| // interpret is a token, then we treat the symbol name as the token. |
| return isSymbolRefExpr(); |
| } |
| |
| bool isSymbolRefExpr() const { |
| return isExpr() && Expr && isa<MCSymbolRefExpr>(Expr); |
| } |
| |
| bool isImm() const override { |
| return Kind == Immediate; |
| } |
| |
| void setImmKindNone() const { |
| assert(isImm()); |
| Imm.Kind = ImmKindTyNone; |
| } |
| |
| void setImmKindLiteral() const { |
| assert(isImm()); |
| Imm.Kind = ImmKindTyLiteral; |
| } |
| |
| void setImmKindConst() const { |
| assert(isImm()); |
| Imm.Kind = ImmKindTyConst; |
| } |
| |
| bool IsImmKindLiteral() const { |
| return isImm() && Imm.Kind == ImmKindTyLiteral; |
| } |
| |
| bool isImmKindConst() const { |
| return isImm() && Imm.Kind == ImmKindTyConst; |
| } |
| |
| bool isInlinableImm(MVT type) const; |
| bool isLiteralImm(MVT type) const; |
| |
| bool isRegKind() const { |
| return Kind == Register; |
| } |
| |
| bool isReg() const override { |
| return isRegKind() && !hasModifiers(); |
| } |
| |
| bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const { |
| return isRegClass(RCID) || isInlinableImm(type) || isLiteralImm(type); |
| } |
| |
| bool isRegOrImmWithInt16InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16); |
| } |
| |
| bool isRegOrImmWithInt32InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32); |
| } |
| |
| bool isRegOrImmWithInt64InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); |
| } |
| |
| bool isRegOrImmWithFP16InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); |
| } |
| |
| bool isRegOrImmWithFP32InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32); |
| } |
| |
| bool isRegOrImmWithFP64InputMods() const { |
| return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64); |
| } |
| |
| bool isVReg() const { |
| return isRegClass(AMDGPU::VGPR_32RegClassID) || |
| isRegClass(AMDGPU::VReg_64RegClassID) || |
| isRegClass(AMDGPU::VReg_96RegClassID) || |
| isRegClass(AMDGPU::VReg_128RegClassID) || |
| isRegClass(AMDGPU::VReg_160RegClassID) || |
| isRegClass(AMDGPU::VReg_192RegClassID) || |
| isRegClass(AMDGPU::VReg_256RegClassID) || |
| isRegClass(AMDGPU::VReg_512RegClassID) || |
| isRegClass(AMDGPU::VReg_1024RegClassID); |
| } |
| |
| bool isVReg32() const { |
| return isRegClass(AMDGPU::VGPR_32RegClassID); |
| } |
| |
| bool isVReg32OrOff() const { |
| return isOff() || isVReg32(); |
| } |
| |
| bool isNull() const { |
| return isRegKind() && getReg() == AMDGPU::SGPR_NULL; |
| } |
| |
| bool isVRegWithInputMods() const; |
| |
| bool isSDWAOperand(MVT type) const; |
| bool isSDWAFP16Operand() const; |
| bool isSDWAFP32Operand() const; |
| bool isSDWAInt16Operand() const; |
| bool isSDWAInt32Operand() const; |
| |
| bool isImmTy(ImmTy ImmT) const { |
| return isImm() && Imm.Type == ImmT; |
| } |
| |
| bool isImmModifier() const { |
| return isImm() && Imm.Type != ImmTyNone; |
| } |
| |
| bool isClampSI() const { return isImmTy(ImmTyClampSI); } |
| bool isOModSI() const { return isImmTy(ImmTyOModSI); } |
| bool isDMask() const { return isImmTy(ImmTyDMask); } |
| bool isDim() const { return isImmTy(ImmTyDim); } |
| bool isUNorm() const { return isImmTy(ImmTyUNorm); } |
| bool isDA() const { return isImmTy(ImmTyDA); } |
| bool isR128A16() const { return isImmTy(ImmTyR128A16); } |
| bool isGFX10A16() const { return isImmTy(ImmTyA16); } |
| bool isLWE() const { return isImmTy(ImmTyLWE); } |
| bool isOff() const { return isImmTy(ImmTyOff); } |
| bool isExpTgt() const { return isImmTy(ImmTyExpTgt); } |
| bool isExpVM() const { return isImmTy(ImmTyExpVM); } |
| bool isExpCompr() const { return isImmTy(ImmTyExpCompr); } |
| bool isOffen() const { return isImmTy(ImmTyOffen); } |
| bool isIdxen() const { return isImmTy(ImmTyIdxen); } |
| bool isAddr64() const { return isImmTy(ImmTyAddr64); } |
| bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); } |
| bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); } |
| bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } |
| |
| bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); } |
| bool isGDS() const { return isImmTy(ImmTyGDS); } |
| bool isLDS() const { return isImmTy(ImmTyLDS); } |
| bool isCPol() const { return isImmTy(ImmTyCPol); } |
| bool isSWZ() const { return isImmTy(ImmTySWZ); } |
| bool isTFE() const { return isImmTy(ImmTyTFE); } |
| bool isD16() const { return isImmTy(ImmTyD16); } |
| bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); } |
| bool isBankMask() const { return isImmTy(ImmTyDppBankMask); } |
| bool isRowMask() const { return isImmTy(ImmTyDppRowMask); } |
| bool isBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); } |
| bool isFI() const { return isImmTy(ImmTyDppFi); } |
| bool isSDWADstSel() const { return isImmTy(ImmTySdwaDstSel); } |
| bool isSDWASrc0Sel() const { return isImmTy(ImmTySdwaSrc0Sel); } |
| bool isSDWASrc1Sel() const { return isImmTy(ImmTySdwaSrc1Sel); } |
| bool isSDWADstUnused() const { return isImmTy(ImmTySdwaDstUnused); } |
| bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); } |
| bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); } |
| bool isAttrChan() const { return isImmTy(ImmTyAttrChan); } |
| bool isOpSel() const { return isImmTy(ImmTyOpSel); } |
| bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); } |
| bool isNegLo() const { return isImmTy(ImmTyNegLo); } |
| bool isNegHi() const { return isImmTy(ImmTyNegHi); } |
| bool isHigh() const { return isImmTy(ImmTyHigh); } |
| |
| bool isMod() const { |
| return isClampSI() || isOModSI(); |
| } |
| |
| bool isRegOrImm() const { |
| return isReg() || isImm(); |
| } |
| |
| bool isRegClass(unsigned RCID) const; |
| |
| bool isInlineValue() const; |
| |
| bool isRegOrInlineNoMods(unsigned RCID, MVT type) const { |
| return (isRegClass(RCID) || isInlinableImm(type)) && !hasModifiers(); |
| } |
| |
| bool isSCSrcB16() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16); |
| } |
| |
| bool isSCSrcV2B16() const { |
| return isSCSrcB16(); |
| } |
| |
| bool isSCSrcB32() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32); |
| } |
| |
| bool isSCSrcB64() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); |
| } |
| |
| bool isBoolReg() const; |
| |
| bool isSCSrcF16() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); |
| } |
| |
| bool isSCSrcV2F16() const { |
| return isSCSrcF16(); |
| } |
| |
| bool isSCSrcF32() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32); |
| } |
| |
| bool isSCSrcF64() const { |
| return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64); |
| } |
| |
| bool isSSrcB32() const { |
| return isSCSrcB32() || isLiteralImm(MVT::i32) || isExpr(); |
| } |
| |
| bool isSSrcB16() const { |
| return isSCSrcB16() || isLiteralImm(MVT::i16); |
| } |
| |
| bool isSSrcV2B16() const { |
| llvm_unreachable("cannot happen"); |
| return isSSrcB16(); |
| } |
| |
| bool isSSrcB64() const { |
| // TODO: Find out how SALU supports extension of 32-bit literals to 64 bits. |
| // See isVSrc64(). |
| return isSCSrcB64() || isLiteralImm(MVT::i64); |
| } |
| |
| bool isSSrcF32() const { |
| return isSCSrcB32() || isLiteralImm(MVT::f32) || isExpr(); |
| } |
| |
| bool isSSrcF64() const { |
| return isSCSrcB64() || isLiteralImm(MVT::f64); |
| } |
| |
| bool isSSrcF16() const { |
| return isSCSrcB16() || isLiteralImm(MVT::f16); |
| } |
| |
| bool isSSrcV2F16() const { |
| llvm_unreachable("cannot happen"); |
| return isSSrcF16(); |
| } |
| |
| bool isSSrcV2FP32() const { |
| llvm_unreachable("cannot happen"); |
| return isSSrcF32(); |
| } |
| |
| bool isSCSrcV2FP32() const { |
| llvm_unreachable("cannot happen"); |
| return isSCSrcF32(); |
| } |
| |
| bool isSSrcV2INT32() const { |
| llvm_unreachable("cannot happen"); |
| return isSSrcB32(); |
| } |
| |
| bool isSCSrcV2INT32() const { |
| llvm_unreachable("cannot happen"); |
| return isSCSrcB32(); |
| } |
| |
| bool isSSrcOrLdsB32() const { |
| return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) || |
| isLiteralImm(MVT::i32) || isExpr(); |
| } |
| |
| bool isVCSrcB32() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32); |
| } |
| |
| bool isVCSrcB64() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); |
| } |
| |
| bool isVCSrcB16() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16); |
| } |
| |
| bool isVCSrcV2B16() const { |
| return isVCSrcB16(); |
| } |
| |
| bool isVCSrcF32() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32); |
| } |
| |
| bool isVCSrcF64() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64); |
| } |
| |
| bool isVCSrcF16() const { |
| return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); |
| } |
| |
| bool isVCSrcV2F16() const { |
| return isVCSrcF16(); |
| } |
| |
| bool isVSrcB32() const { |
| return isVCSrcF32() || isLiteralImm(MVT::i32) || isExpr(); |
| } |
| |
| bool isVSrcB64() const { |
| return isVCSrcF64() || isLiteralImm(MVT::i64); |
| } |
| |
| bool isVSrcB16() const { |
| return isVCSrcB16() || isLiteralImm(MVT::i16); |
| } |
| |
| bool isVSrcV2B16() const { |
| return isVSrcB16() || isLiteralImm(MVT::v2i16); |
| } |
| |
| bool isVCSrcV2FP32() const { |
| return isVCSrcF64(); |
| } |
| |
| bool isVSrcV2FP32() const { |
| return isVSrcF64() || isLiteralImm(MVT::v2f32); |
| } |
| |
| bool isVCSrcV2INT32() const { |
| return isVCSrcB64(); |
| } |
| |
| bool isVSrcV2INT32() const { |
| return isVSrcB64() || isLiteralImm(MVT::v2i32); |
| } |
| |
| bool isVSrcF32() const { |
| return isVCSrcF32() || isLiteralImm(MVT::f32) || isExpr(); |
| } |
| |
| bool isVSrcF64() const { |
| return isVCSrcF64() || isLiteralImm(MVT::f64); |
| } |
| |
| bool isVSrcF16() const { |
| return isVCSrcF16() || isLiteralImm(MVT::f16); |
| } |
| |
| bool isVSrcV2F16() const { |
| return isVSrcF16() || isLiteralImm(MVT::v2f16); |
| } |
| |
| bool isVISrcB32() const { |
| return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32); |
| } |
| |
| bool isVISrcB16() const { |
| return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16); |
| } |
| |
| bool isVISrcV2B16() const { |
| return isVISrcB16(); |
| } |
| |
| bool isVISrcF32() const { |
| return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32); |
| } |
| |
| bool isVISrcF16() const { |
| return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); |
| } |
| |
| bool isVISrcV2F16() const { |
| return isVISrcF16() || isVISrcB32(); |
| } |
| |
| bool isVISrc_64B64() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64); |
| } |
| |
| bool isVISrc_64F64() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64); |
| } |
| |
| bool isVISrc_64V2FP32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32); |
| } |
| |
| bool isVISrc_64V2INT32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32); |
| } |
| |
| bool isVISrc_256B64() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64); |
| } |
| |
| bool isVISrc_256F64() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64); |
| } |
| |
| bool isVISrc_128B16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16); |
| } |
| |
| bool isVISrc_128V2B16() const { |
| return isVISrc_128B16(); |
| } |
| |
| bool isVISrc_128B32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32); |
| } |
| |
| bool isVISrc_128F32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32); |
| } |
| |
| bool isVISrc_256V2FP32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32); |
| } |
| |
| bool isVISrc_256V2INT32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32); |
| } |
| |
| bool isVISrc_512B32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32); |
| } |
| |
| bool isVISrc_512B16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16); |
| } |
| |
| bool isVISrc_512V2B16() const { |
| return isVISrc_512B16(); |
| } |
| |
| bool isVISrc_512F32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32); |
| } |
| |
| bool isVISrc_512F16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16); |
| } |
| |
| bool isVISrc_512V2F16() const { |
| return isVISrc_512F16() || isVISrc_512B32(); |
| } |
| |
| bool isVISrc_1024B32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32); |
| } |
| |
| bool isVISrc_1024B16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16); |
| } |
| |
| bool isVISrc_1024V2B16() const { |
| return isVISrc_1024B16(); |
| } |
| |
| bool isVISrc_1024F32() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32); |
| } |
| |
| bool isVISrc_1024F16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16); |
| } |
| |
| bool isVISrc_1024V2F16() const { |
| return isVISrc_1024F16() || isVISrc_1024B32(); |
| } |
| |
| bool isAISrcB32() const { |
| return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32); |
| } |
| |
| bool isAISrcB16() const { |
| return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16); |
| } |
| |
| bool isAISrcV2B16() const { |
| return isAISrcB16(); |
| } |
| |
| bool isAISrcF32() const { |
| return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32); |
| } |
| |
| bool isAISrcF16() const { |
| return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); |
| } |
| |
| bool isAISrcV2F16() const { |
| return isAISrcF16() || isAISrcB32(); |
| } |
| |
| bool isAISrc_64B64() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64); |
| } |
| |
| bool isAISrc_64F64() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64); |
| } |
| |
| bool isAISrc_128B32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32); |
| } |
| |
| bool isAISrc_128B16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16); |
| } |
| |
| bool isAISrc_128V2B16() const { |
| return isAISrc_128B16(); |
| } |
| |
| bool isAISrc_128F32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32); |
| } |
| |
| bool isAISrc_128F16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); |
| } |
| |
| bool isAISrc_128V2F16() const { |
| return isAISrc_128F16() || isAISrc_128B32(); |
| } |
| |
| bool isVISrc_128F16() const { |
| return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16); |
| } |
| |
| bool isVISrc_128V2F16() const { |
| return isVISrc_128F16() || isVISrc_128B32(); |
| } |
| |
| bool isAISrc_256B64() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64); |
| } |
| |
| bool isAISrc_256F64() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64); |
| } |
| |
| bool isAISrc_512B32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32); |
| } |
| |
| bool isAISrc_512B16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16); |
| } |
| |
| bool isAISrc_512V2B16() const { |
| return isAISrc_512B16(); |
| } |
| |
| bool isAISrc_512F32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32); |
| } |
| |
| bool isAISrc_512F16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); |
| } |
| |
| bool isAISrc_512V2F16() const { |
| return isAISrc_512F16() || isAISrc_512B32(); |
| } |
| |
| bool isAISrc_1024B32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32); |
| } |
| |
| bool isAISrc_1024B16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16); |
| } |
| |
| bool isAISrc_1024V2B16() const { |
| return isAISrc_1024B16(); |
| } |
| |
| bool isAISrc_1024F32() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32); |
| } |
| |
| bool isAISrc_1024F16() const { |
| return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); |
| } |
| |
| bool isAISrc_1024V2F16() const { |
| return isAISrc_1024F16() || isAISrc_1024B32(); |
| } |
| |
| bool isKImmFP32() const { |
| return isLiteralImm(MVT::f32); |
| } |
| |
| bool isKImmFP16() const { |
| return isLiteralImm(MVT::f16); |
| } |
| |
| bool isMem() const override { |
| return false; |
| } |
| |
| bool isExpr() const { |
| return Kind == Expression; |
| } |
| |
| bool isSoppBrTarget() const { |
| return isExpr() || isImm(); |
| } |
| |
| bool isSWaitCnt() const; |
| bool isHwreg() const; |
| bool isSendMsg() const; |
| bool isSwizzle() const; |
| bool isSMRDOffset8() const; |
| bool isSMEMOffset() const; |
| bool isSMRDLiteralOffset() const; |
| bool isDPP8() const; |
| bool isDPPCtrl() const; |
| bool isBLGP() const; |
| bool isCBSZ() const; |
| bool isABID() const; |
| bool isGPRIdxMode() const; |
| bool isS16Imm() const; |
| bool isU16Imm() const; |
| bool isEndpgm() const; |
| |
| StringRef getExpressionAsToken() const { |
| assert(isExpr()); |
| const MCSymbolRefExpr *S = cast<MCSymbolRefExpr>(Expr); |
| return S->getSymbol().getName(); |
| } |
| |
| StringRef getToken() const { |
| assert(isToken()); |
| |
| if (Kind == Expression) |
| return getExpressionAsToken(); |
| |
| return StringRef(Tok.Data, Tok.Length); |
| } |
| |
| int64_t getImm() const { |
| assert(isImm()); |
| return Imm.Val; |
| } |
| |
| void setImm(int64_t Val) { |
| assert(isImm()); |
| Imm.Val = Val; |
| } |
| |
| ImmTy getImmTy() const { |
| assert(isImm()); |
| return Imm.Type; |
| } |
| |
| unsigned getReg() const override { |
| assert(isRegKind()); |
| return Reg.RegNo; |
| } |
| |
| SMLoc getStartLoc() const override { |
| return StartLoc; |
| } |
| |
| SMLoc getEndLoc() const override { |
| return EndLoc; |
| } |
| |
| SMRange getLocRange() const { |
| return SMRange(StartLoc, EndLoc); |
| } |
| |
| Modifiers getModifiers() const { |
| assert(isRegKind() || isImmTy(ImmTyNone)); |
| return isRegKind() ? Reg.Mods : Imm.Mods; |
| } |
| |
| void setModifiers(Modifiers Mods) { |
| assert(isRegKind() || isImmTy(ImmTyNone)); |
| if (isRegKind()) |
| Reg.Mods = Mods; |
| else |
| Imm.Mods = Mods; |
| } |
| |
| bool hasModifiers() const { |
| return getModifiers().hasModifiers(); |
| } |
| |
| bool hasFPModifiers() const { |
| return getModifiers().hasFPModifiers(); |
| } |
| |
| bool hasIntModifiers() const { |
| return getModifiers().hasIntModifiers(); |
| } |
| |
| uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const; |
| |
| void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const; |
| |
| void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const; |
| |
| template <unsigned Bitwidth> |
| void addKImmFPOperands(MCInst &Inst, unsigned N) const; |
| |
| void addKImmFP16Operands(MCInst &Inst, unsigned N) const { |
| addKImmFPOperands<16>(Inst, N); |
| } |
| |
| void addKImmFP32Operands(MCInst &Inst, unsigned N) const { |
| addKImmFPOperands<32>(Inst, N); |
| } |
| |
| void addRegOperands(MCInst &Inst, unsigned N) const; |
| |
| void addBoolRegOperands(MCInst &Inst, unsigned N) const { |
| addRegOperands(Inst, N); |
| } |
| |
| void addRegOrImmOperands(MCInst &Inst, unsigned N) const { |
| if (isRegKind()) |
| addRegOperands(Inst, N); |
| else if (isExpr()) |
| Inst.addOperand(MCOperand::createExpr(Expr)); |
| else |
| addImmOperands(Inst, N); |
| } |
| |
| void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const { |
| Modifiers Mods = getModifiers(); |
| Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand())); |
| if (isRegKind()) { |
| addRegOperands(Inst, N); |
| } else { |
| addImmOperands(Inst, N, false); |
| } |
| } |
| |
| void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const { |
| assert(!hasIntModifiers()); |
| addRegOrImmWithInputModsOperands(Inst, N); |
| } |
| |
| void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const { |
| assert(!hasFPModifiers()); |
| addRegOrImmWithInputModsOperands(Inst, N); |
| } |
| |
| void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const { |
| Modifiers Mods = getModifiers(); |
| Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand())); |
| assert(isRegKind()); |
| addRegOperands(Inst, N); |
| } |
| |
| void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const { |
| assert(!hasIntModifiers()); |
| addRegWithInputModsOperands(Inst, N); |
| } |
| |
| void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const { |
| assert(!hasFPModifiers()); |
| addRegWithInputModsOperands(Inst, N); |
| } |
| |
| void addSoppBrTargetOperands(MCInst &Inst, unsigned N) const { |
| if (isImm()) |
| addImmOperands(Inst, N); |
| else { |
| assert(isExpr()); |
| Inst.addOperand(MCOperand::createExpr(Expr)); |
| } |
| } |
| |
| static void printImmTy(raw_ostream& OS, ImmTy Type) { |
| switch (Type) { |
| case ImmTyNone: OS << "None"; break; |
| case ImmTyGDS: OS << "GDS"; break; |
| case ImmTyLDS: OS << "LDS"; break; |
| case ImmTyOffen: OS << "Offen"; break; |
| case ImmTyIdxen: OS << "Idxen"; break; |
| case ImmTyAddr64: OS << "Addr64"; break; |
| case ImmTyOffset: OS << "Offset"; break; |
| case ImmTyInstOffset: OS << "InstOffset"; break; |
| case ImmTyOffset0: OS << "Offset0"; break; |
| case ImmTyOffset1: OS << "Offset1"; break; |
| case ImmTyCPol: OS << "CPol"; break; |
| case ImmTySWZ: OS << "SWZ"; break; |
| case ImmTyTFE: OS << "TFE"; break; |
| case ImmTyD16: OS << "D16"; break; |
| case ImmTyFORMAT: OS << "FORMAT"; break; |
| case ImmTyClampSI: OS << "ClampSI"; break; |
| case ImmTyOModSI: OS << "OModSI"; break; |
| case ImmTyDPP8: OS << "DPP8"; break; |
| case ImmTyDppCtrl: OS << "DppCtrl"; break; |
| case ImmTyDppRowMask: OS << "DppRowMask"; break; |
| case ImmTyDppBankMask: OS << "DppBankMask"; break; |
| case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break; |
| case ImmTyDppFi: OS << "FI"; break; |
| case ImmTySdwaDstSel: OS << "SdwaDstSel"; break; |
| case ImmTySdwaSrc0Sel: OS << "SdwaSrc0Sel"; break; |
| case ImmTySdwaSrc1Sel: OS << "SdwaSrc1Sel"; break; |
| case ImmTySdwaDstUnused: OS << "SdwaDstUnused"; break; |
| case ImmTyDMask: OS << "DMask"; break; |
| case ImmTyDim: OS << "Dim"; break; |
| case ImmTyUNorm: OS << "UNorm"; break; |
| case ImmTyDA: OS << "DA"; break; |
| case ImmTyR128A16: OS << "R128A16"; break; |
| case ImmTyA16: OS << "A16"; break; |
| case ImmTyLWE: OS << "LWE"; break; |
| case ImmTyOff: OS << "Off"; break; |
| case ImmTyExpTgt: OS << "ExpTgt"; break; |
| case ImmTyExpCompr: OS << "ExpCompr"; break; |
| case ImmTyExpVM: OS << "ExpVM"; break; |
| case ImmTyHwreg: OS << "Hwreg"; break; |
| case ImmTySendMsg: OS << "SendMsg"; break; |
| case ImmTyInterpSlot: OS << "InterpSlot"; break; |
| case ImmTyInterpAttr: OS << "InterpAttr"; break; |
| case ImmTyAttrChan: OS << "AttrChan"; break; |
| case ImmTyOpSel: OS << "OpSel"; break; |
| case ImmTyOpSelHi: OS << "OpSelHi"; break; |
| case ImmTyNegLo: OS << "NegLo"; break; |
| case ImmTyNegHi: OS << "NegHi"; break; |
| case ImmTySwizzle: OS << "Swizzle"; break; |
| case ImmTyGprIdxMode: OS << "GprIdxMode"; break; |
| case ImmTyHigh: OS << "High"; break; |
| case ImmTyBLGP: OS << "BLGP"; break; |
| case ImmTyCBSZ: OS << "CBSZ"; break; |
| case ImmTyABID: OS << "ABID"; break; |
| case ImmTyEndpgm: OS << "Endpgm"; break; |
| } |
| } |
| |
| void print(raw_ostream &OS) const override { |
| switch (Kind) { |
| case Register: |
| OS << "<register " << getReg() << " mods: " << Reg.Mods << '>'; |
| break; |
| case Immediate: |
| OS << '<' << getImm(); |
| if (getImmTy() != ImmTyNone) { |
| OS << " type: "; printImmTy(OS, getImmTy()); |
| } |
| OS << " mods: " << Imm.Mods << '>'; |
| break; |
| case Token: |
| OS << '\'' << getToken() << '\''; |
| break; |
| case Expression: |
| OS << "<expr " << *Expr << '>'; |
| break; |
| } |
| } |
| |
| static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser, |
| int64_t Val, SMLoc Loc, |
| ImmTy Type = ImmTyNone, |
| bool IsFPImm = false) { |
| auto Op = std::make_unique<AMDGPUOperand>(Immediate, AsmParser); |
| Op->Imm.Val = Val; |
| Op->Imm.IsFPImm = IsFPImm; |
| Op->Imm.Kind = ImmKindTyNone; |
| Op->Imm.Type = Type; |
| Op->Imm.Mods = Modifiers(); |
| Op->StartLoc = Loc; |
| Op->EndLoc = Loc; |
| return Op; |
| } |
| |
| static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser, |
| StringRef Str, SMLoc Loc, |
| bool HasExplicitEncodingSize = true) { |
| auto Res = std::make_unique<AMDGPUOperand>(Token, AsmParser); |
| Res->Tok.Data = Str.data(); |
| Res->Tok.Length = Str.size(); |
| Res->StartLoc = Loc; |
| Res->EndLoc = Loc; |
| return Res; |
| } |
| |
| static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser, |
| unsigned RegNo, SMLoc S, |
| SMLoc E) { |
| auto Op = std::make_unique<AMDGPUOperand>(Register, AsmParser); |
| Op->Reg.RegNo = RegNo; |
| Op->Reg.Mods = Modifiers(); |
| Op->StartLoc = S; |
| Op->EndLoc = E; |
| return Op; |
| } |
| |
| static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser, |
| const class MCExpr *Expr, SMLoc S) { |
| auto Op = std::make_unique<AMDGPUOperand>(Expression, AsmParser); |
| Op->Expr = Expr; |
| Op->StartLoc = S; |
| Op->EndLoc = S; |
| return Op; |
| } |
| }; |
| |
| raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) { |
| OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext; |
| return OS; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // AsmParser |
| //===----------------------------------------------------------------------===// |
| |
| // Holds info related to the current kernel, e.g. count of SGPRs used. |
| // Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next |
| // .amdgpu_hsa_kernel or at EOF. |
| class KernelScopeInfo { |
| int SgprIndexUnusedMin = -1; |
| int VgprIndexUnusedMin = -1; |
| MCContext *Ctx = nullptr; |
| |
| void usesSgprAt(int i) { |
| if (i >= SgprIndexUnusedMin) { |
| SgprIndexUnusedMin = ++i; |
| if (Ctx) { |
| MCSymbol * const Sym = Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count")); |
| Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx)); |
| } |
| } |
| } |
| |
| void usesVgprAt(int i) { |
| if (i >= VgprIndexUnusedMin) { |
| VgprIndexUnusedMin = ++i; |
| if (Ctx) { |
| MCSymbol * const Sym = Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count")); |
| Sym->setVariableValue(MCConstantExpr::create(VgprIndexUnusedMin, *Ctx)); |
| } |
| } |
| } |
| |
| public: |
| KernelScopeInfo() = default; |
| |
| void initialize(MCContext &Context) { |
| Ctx = &Context; |
| usesSgprAt(SgprIndexUnusedMin = -1); |
| usesVgprAt(VgprIndexUnusedMin = -1); |
| } |
| |
| void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { |
| switch (RegKind) { |
| case IS_SGPR: usesSgprAt(DwordRegIndex + RegWidth - 1); break; |
| case IS_AGPR: // fall through |
| case IS_VGPR: usesVgprAt(DwordRegIndex + RegWidth - 1); break; |
| default: break; |
| } |
| } |
| }; |
| |
| class AMDGPUAsmParser : public MCTargetAsmParser { |
| MCAsmParser &Parser; |
| |
| // Number of extra operands parsed after the first optional operand. |
| // This may be necessary to skip hardcoded mandatory operands. |
| static const unsigned MAX_OPR_LOOKAHEAD = 8; |
| |
| unsigned ForcedEncodingSize = 0; |
| bool ForcedDPP = false; |
| bool ForcedSDWA = false; |
| KernelScopeInfo KernelScope; |
| unsigned CPolSeen; |
| |
| /// @name Auto-generated Match Functions |
| /// { |
| |
| #define GET_ASSEMBLER_HEADER |
| #include "AMDGPUGenAsmMatcher.inc" |
| |
| /// } |
| |
| private: |
| bool ParseAsAbsoluteExpression(uint32_t &Ret); |
| bool OutOfRangeError(SMRange Range); |
| /// Calculate VGPR/SGPR blocks required for given target, reserved |
| /// registers, and user-specified NextFreeXGPR values. |
| /// |
| /// \param Features [in] Target features, used for bug corrections. |
| /// \param VCCUsed [in] Whether VCC special SGPR is reserved. |
| /// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved. |
| /// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved. |
| /// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel |
| /// descriptor field, if valid. |
| /// \param NextFreeVGPR [in] Max VGPR number referenced, plus one. |
| /// \param VGPRRange [in] Token range, used for VGPR diagnostics. |
| /// \param NextFreeSGPR [in] Max SGPR number referenced, plus one. |
| /// \param SGPRRange [in] Token range, used for SGPR diagnostics. |
| /// \param VGPRBlocks [out] Result VGPR block count. |
| /// \param SGPRBlocks [out] Result SGPR block count. |
| bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed, |
| bool FlatScrUsed, bool XNACKUsed, |
| Optional<bool> EnableWavefrontSize32, unsigned NextFreeVGPR, |
| SMRange VGPRRange, unsigned NextFreeSGPR, |
| SMRange SGPRRange, unsigned &VGPRBlocks, |
| unsigned &SGPRBlocks); |
| bool ParseDirectiveAMDGCNTarget(); |
| bool ParseDirectiveAMDHSAKernel(); |
| bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor); |
| bool ParseDirectiveHSACodeObjectVersion(); |
| bool ParseDirectiveHSACodeObjectISA(); |
| bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header); |
| bool ParseDirectiveAMDKernelCodeT(); |
| // TODO: Possibly make subtargetHasRegister const. |
| bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo); |
| bool ParseDirectiveAMDGPUHsaKernel(); |
| |
| bool ParseDirectiveISAVersion(); |
| bool ParseDirectiveHSAMetadata(); |
| bool ParseDirectivePALMetadataBegin(); |
| bool ParseDirectivePALMetadata(); |
| bool ParseDirectiveAMDGPULDS(); |
| |
| /// Common code to parse out a block of text (typically YAML) between start and |
| /// end directives. |
| bool ParseToEndDirective(const char *AssemblerDirectiveBegin, |
| const char *AssemblerDirectiveEnd, |
| std::string &CollectString); |
| |
| bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, |
| RegisterKind RegKind, unsigned Reg1, SMLoc Loc); |
| bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, |
| unsigned &RegNum, unsigned &RegWidth, |
| bool RestoreOnFailure = false); |
| bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, |
| unsigned &RegNum, unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens); |
| unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum, |
| unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens); |
| unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum, |
| unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens); |
| unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum, |
| unsigned &RegWidth, SmallVectorImpl<AsmToken> &Tokens); |
| bool ParseRegRange(unsigned& Num, unsigned& Width); |
| unsigned getRegularReg(RegisterKind RegKind, |
| unsigned RegNum, |
| unsigned RegWidth, |
| SMLoc Loc); |
| |
| bool isRegister(); |
| bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const; |
| Optional<StringRef> getGprCountSymbolName(RegisterKind RegKind); |
| void initializeGprCountSymbol(RegisterKind RegKind); |
| bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex, |
| unsigned RegWidth); |
| void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands, |
| bool IsAtomic, bool IsLds = false); |
| void cvtDSImpl(MCInst &Inst, const OperandVector &Operands, |
| bool IsGdsHardcoded); |
| |
| public: |
| enum AMDGPUMatchResultTy { |
| Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY |
| }; |
| enum OperandMode { |
| OperandMode_Default, |
| OperandMode_NSA, |
| }; |
| |
| using OptionalImmIndexMap = std::map<AMDGPUOperand::ImmTy, unsigned>; |
| |
| AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser, |
| const MCInstrInfo &MII, |
| const MCTargetOptions &Options) |
| : MCTargetAsmParser(Options, STI, MII), Parser(_Parser) { |
| MCAsmParserExtension::Initialize(Parser); |
| |
| if (getFeatureBits().none()) { |
| // Set default features. |
| copySTI().ToggleFeature("southern-islands"); |
| } |
| |
| setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits())); |
| |
| { |
| // TODO: make those pre-defined variables read-only. |
| // Currently there is none suitable machinery in the core llvm-mc for this. |
| // MCSymbol::isRedefinable is intended for another purpose, and |
| // AsmParser::parseDirectiveSet() cannot be specialized for specific target. |
| AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU()); |
| MCContext &Ctx = getContext(); |
| if (ISA.Major >= 6 && isHsaAbiVersion3Or4(&getSTI())) { |
| MCSymbol *Sym = |
| Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx)); |
| Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx)); |
| Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx)); |
| } else { |
| MCSymbol *Sym = |
| Ctx.getOrCreateSymbol(Twine(".option.machine_version_major")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx)); |
| Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx)); |
| Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping")); |
| Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx)); |
| } |
| if (ISA.Major >= 6 && isHsaAbiVersion3Or4(&getSTI())) { |
| initializeGprCountSymbol(IS_VGPR); |
| initializeGprCountSymbol(IS_SGPR); |
| } else |
| KernelScope.initialize(getContext()); |
| } |
| } |
| |
| bool hasMIMG_R128() const { |
| return AMDGPU::hasMIMG_R128(getSTI()); |
| } |
| |
| bool hasPackedD16() const { |
| return AMDGPU::hasPackedD16(getSTI()); |
| } |
| |
| bool hasGFX10A16() const { |
| return AMDGPU::hasGFX10A16(getSTI()); |
| } |
| |
| bool hasG16() const { return AMDGPU::hasG16(getSTI()); } |
| |
| bool isSI() const { |
| return AMDGPU::isSI(getSTI()); |
| } |
| |
| bool isCI() const { |
| return AMDGPU::isCI(getSTI()); |
| } |
| |
| bool isVI() const { |
| return AMDGPU::isVI(getSTI()); |
| } |
| |
| bool isGFX9() const { |
| return AMDGPU::isGFX9(getSTI()); |
| } |
| |
| bool isGFX90A() const { |
| return AMDGPU::isGFX90A(getSTI()); |
| } |
| |
| bool isGFX9Plus() const { |
| return AMDGPU::isGFX9Plus(getSTI()); |
| } |
| |
| bool isGFX10() const { |
| return AMDGPU::isGFX10(getSTI()); |
| } |
| |
| bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); } |
| |
| bool isGFX10_BEncoding() const { |
| return AMDGPU::isGFX10_BEncoding(getSTI()); |
| } |
| |
| bool hasInv2PiInlineImm() const { |
| return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm]; |
| } |
| |
| bool hasFlatOffsets() const { |
| return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets]; |
| } |
| |
| bool hasArchitectedFlatScratch() const { |
| return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; |
| } |
| |
| bool hasSGPR102_SGPR103() const { |
| return !isVI() && !isGFX9(); |
| } |
| |
| bool hasSGPR104_SGPR105() const { return isGFX10Plus(); } |
| |
| bool hasIntClamp() const { |
| return getFeatureBits()[AMDGPU::FeatureIntClamp]; |
| } |
| |
| AMDGPUTargetStreamer &getTargetStreamer() { |
| MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); |
| return static_cast<AMDGPUTargetStreamer &>(TS); |
| } |
| |
| const MCRegisterInfo *getMRI() const { |
| // We need this const_cast because for some reason getContext() is not const |
| // in MCAsmParser. |
| return const_cast<AMDGPUAsmParser*>(this)->getContext().getRegisterInfo(); |
| } |
| |
| const MCInstrInfo *getMII() const { |
| return &MII; |
| } |
| |
| const FeatureBitset &getFeatureBits() const { |
| return getSTI().getFeatureBits(); |
| } |
| |
| void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; } |
| void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; } |
| void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; } |
| |
| unsigned getForcedEncodingSize() const { return ForcedEncodingSize; } |
| bool isForcedVOP3() const { return ForcedEncodingSize == 64; } |
| bool isForcedDPP() const { return ForcedDPP; } |
| bool isForcedSDWA() const { return ForcedSDWA; } |
| ArrayRef<unsigned> getMatchedVariants() const; |
| StringRef getMatchedVariantName() const; |
| |
| std::unique_ptr<AMDGPUOperand> parseRegister(bool RestoreOnFailure = false); |
| bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, |
| bool RestoreOnFailure); |
| bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; |
| OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, |
| SMLoc &EndLoc) override; |
| unsigned checkTargetMatchPredicate(MCInst &Inst) override; |
| unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, |
| unsigned Kind) override; |
| bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, |
| OperandVector &Operands, MCStreamer &Out, |
| uint64_t &ErrorInfo, |
| bool MatchingInlineAsm) override; |
| bool ParseDirective(AsmToken DirectiveID) override; |
| OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic, |
| OperandMode Mode = OperandMode_Default); |
| StringRef parseMnemonicSuffix(StringRef Name); |
| bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, |
| SMLoc NameLoc, OperandVector &Operands) override; |
| //bool ProcessInstruction(MCInst &Inst); |
| |
| OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int); |
| |
| OperandMatchResultTy |
| parseIntWithPrefix(const char *Prefix, OperandVector &Operands, |
| AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone, |
| bool (*ConvertResult)(int64_t &) = nullptr); |
| |
| OperandMatchResultTy |
| parseOperandArrayWithPrefix(const char *Prefix, |
| OperandVector &Operands, |
| AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone, |
| bool (*ConvertResult)(int64_t&) = nullptr); |
| |
| OperandMatchResultTy |
| parseNamedBit(StringRef Name, OperandVector &Operands, |
| AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone); |
| OperandMatchResultTy parseCPol(OperandVector &Operands); |
| OperandMatchResultTy parseStringWithPrefix(StringRef Prefix, |
| StringRef &Value, |
| SMLoc &StringLoc); |
| |
| bool isModifier(); |
| bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const; |
| bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const; |
| bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const; |
| bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const; |
| bool parseSP3NegModifier(); |
| OperandMatchResultTy parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false); |
| OperandMatchResultTy parseReg(OperandVector &Operands); |
| OperandMatchResultTy parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false); |
| OperandMatchResultTy parseRegOrImmWithFPInputMods(OperandVector &Operands, bool AllowImm = true); |
| OperandMatchResultTy parseRegOrImmWithIntInputMods(OperandVector &Operands, bool AllowImm = true); |
| OperandMatchResultTy parseRegWithFPInputMods(OperandVector &Operands); |
| OperandMatchResultTy parseRegWithIntInputMods(OperandVector &Operands); |
| OperandMatchResultTy parseVReg32OrOff(OperandVector &Operands); |
| OperandMatchResultTy parseDfmtNfmt(int64_t &Format); |
| OperandMatchResultTy parseUfmt(int64_t &Format); |
| OperandMatchResultTy parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc, int64_t &Format); |
| OperandMatchResultTy parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc, int64_t &Format); |
| OperandMatchResultTy parseFORMAT(OperandVector &Operands); |
| OperandMatchResultTy parseSymbolicOrNumericFormat(int64_t &Format); |
| OperandMatchResultTy parseNumericFormat(int64_t &Format); |
| bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val); |
| bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc); |
| |
| void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands); |
| void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); } |
| void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); } |
| void cvtExp(MCInst &Inst, const OperandVector &Operands); |
| |
| bool parseCnt(int64_t &IntVal); |
| OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands); |
| OperandMatchResultTy parseHwreg(OperandVector &Operands); |
| |
| private: |
| struct OperandInfoTy { |
| SMLoc Loc; |
| int64_t Id; |
| bool IsSymbolic = false; |
| bool IsDefined = false; |
| |
| OperandInfoTy(int64_t Id_) : Id(Id_) {} |
| }; |
| |
| bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream); |
| bool validateSendMsg(const OperandInfoTy &Msg, |
| const OperandInfoTy &Op, |
| const OperandInfoTy &Stream); |
| |
| bool parseHwregBody(OperandInfoTy &HwReg, |
| OperandInfoTy &Offset, |
| OperandInfoTy &Width); |
| bool validateHwreg(const OperandInfoTy &HwReg, |
| const OperandInfoTy &Offset, |
| const OperandInfoTy &Width); |
| |
| SMLoc getFlatOffsetLoc(const OperandVector &Operands) const; |
| SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const; |
| |
| SMLoc getOperandLoc(std::function<bool(const AMDGPUOperand&)> Test, |
| const OperandVector &Operands) const; |
| SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const; |
| SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const; |
| SMLoc getLitLoc(const OperandVector &Operands) const; |
| SMLoc getConstLoc(const OperandVector &Operands) const; |
| |
| bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands); |
| bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands); |
| bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands); |
| bool validateSOPLiteral(const MCInst &Inst) const; |
| bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands); |
| bool validateEarlyClobberLimitations(const MCInst &Inst, const OperandVector &Operands); |
| bool validateIntClampSupported(const MCInst &Inst); |
| bool validateMIMGAtomicDMask(const MCInst &Inst); |
| bool validateMIMGGatherDMask(const MCInst &Inst); |
| bool validateMovrels(const MCInst &Inst, const OperandVector &Operands); |
| bool validateMIMGDataSize(const MCInst &Inst); |
| bool validateMIMGAddrSize(const MCInst &Inst); |
| bool validateMIMGD16(const MCInst &Inst); |
| bool validateMIMGDim(const MCInst &Inst); |
| bool validateMIMGMSAA(const MCInst &Inst); |
| bool validateOpSel(const MCInst &Inst); |
| bool validateDPP(const MCInst &Inst, const OperandVector &Operands); |
| bool validateVccOperand(unsigned Reg) const; |
| bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands); |
| bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands); |
| bool validateAGPRLdSt(const MCInst &Inst) const; |
| bool validateVGPRAlign(const MCInst &Inst) const; |
| bool validateGWS(const MCInst &Inst, const OperandVector &Operands); |
| bool validateDivScale(const MCInst &Inst); |
| bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands, |
| const SMLoc &IDLoc); |
| Optional<StringRef> validateLdsDirect(const MCInst &Inst); |
| unsigned getConstantBusLimit(unsigned Opcode) const; |
| bool usesConstantBus(const MCInst &Inst, unsigned OpIdx); |
| bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const; |
| unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const; |
| |
| bool isSupportedMnemo(StringRef Mnemo, |
| const FeatureBitset &FBS); |
| bool isSupportedMnemo(StringRef Mnemo, |
| const FeatureBitset &FBS, |
| ArrayRef<unsigned> Variants); |
| bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc); |
| |
| bool isId(const StringRef Id) const; |
| bool isId(const AsmToken &Token, const StringRef Id) const; |
| bool isToken(const AsmToken::TokenKind Kind) const; |
| bool trySkipId(const StringRef Id); |
| bool trySkipId(const StringRef Pref, const StringRef Id); |
| bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind); |
| bool trySkipToken(const AsmToken::TokenKind Kind); |
| bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg); |
| bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string"); |
| bool parseId(StringRef &Val, const StringRef ErrMsg = ""); |
| |
| void peekTokens(MutableArrayRef<AsmToken> Tokens); |
| AsmToken::TokenKind getTokenKind() const; |
| bool parseExpr(int64_t &Imm, StringRef Expected = ""); |
| bool parseExpr(OperandVector &Operands); |
| StringRef getTokenStr() const; |
| AsmToken peekToken(); |
| AsmToken getToken() const; |
| SMLoc getLoc() const; |
| void lex(); |
| |
| public: |
| void onBeginOfFile() override; |
| |
| OperandMatchResultTy parseOptionalOperand(OperandVector &Operands); |
| OperandMatchResultTy parseOptionalOpr(OperandVector &Operands); |
| |
| OperandMatchResultTy parseExpTgt(OperandVector &Operands); |
| OperandMatchResultTy parseSendMsgOp(OperandVector &Operands); |
| OperandMatchResultTy parseInterpSlot(OperandVector &Operands); |
| OperandMatchResultTy parseInterpAttr(OperandVector &Operands); |
| OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands); |
| OperandMatchResultTy parseBoolReg(OperandVector &Operands); |
| |
| bool parseSwizzleOperand(int64_t &Op, |
| const unsigned MinVal, |
| const unsigned MaxVal, |
| const StringRef ErrMsg, |
| SMLoc &Loc); |
| bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op, |
| const unsigned MinVal, |
| const unsigned MaxVal, |
| const StringRef ErrMsg); |
| OperandMatchResultTy parseSwizzleOp(OperandVector &Operands); |
| bool parseSwizzleOffset(int64_t &Imm); |
| bool parseSwizzleMacro(int64_t &Imm); |
| bool parseSwizzleQuadPerm(int64_t &Imm); |
| bool parseSwizzleBitmaskPerm(int64_t &Imm); |
| bool parseSwizzleBroadcast(int64_t &Imm); |
| bool parseSwizzleSwap(int64_t &Imm); |
| bool parseSwizzleReverse(int64_t &Imm); |
| |
| OperandMatchResultTy parseGPRIdxMode(OperandVector &Operands); |
| int64_t parseGPRIdxMacro(); |
| |
| void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); } |
| void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); } |
| void cvtMubufLds(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false, true); } |
| void cvtMtbuf(MCInst &Inst, const OperandVector &Operands); |
| |
| AMDGPUOperand::Ptr defaultCPol() const; |
| |
| AMDGPUOperand::Ptr defaultSMRDOffset8() const; |
| AMDGPUOperand::Ptr defaultSMEMOffset() const; |
| AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const; |
| AMDGPUOperand::Ptr defaultFlatOffset() const; |
| |
| OperandMatchResultTy parseOModOperand(OperandVector &Operands); |
| |
| void cvtVOP3(MCInst &Inst, const OperandVector &Operands, |
| OptionalImmIndexMap &OptionalIdx); |
| void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands); |
| void cvtVOP3(MCInst &Inst, const OperandVector &Operands); |
| void cvtVOP3P(MCInst &Inst, const OperandVector &Operands); |
| void cvtVOP3P(MCInst &Inst, const OperandVector &Operands, |
| OptionalImmIndexMap &OptionalIdx); |
| |
| void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands); |
| |
| void cvtMIMG(MCInst &Inst, const OperandVector &Operands, |
| bool IsAtomic = false); |
| void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands); |
| void cvtIntersectRay(MCInst &Inst, const OperandVector &Operands); |
| |
| void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands); |
| |
| bool parseDimId(unsigned &Encoding); |
| OperandMatchResultTy parseDim(OperandVector &Operands); |
| OperandMatchResultTy parseDPP8(OperandVector &Operands); |
| OperandMatchResultTy parseDPPCtrl(OperandVector &Operands); |
| bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands); |
| int64_t parseDPPCtrlSel(StringRef Ctrl); |
| int64_t parseDPPCtrlPerm(); |
| AMDGPUOperand::Ptr defaultRowMask() const; |
| AMDGPUOperand::Ptr defaultBankMask() const; |
| AMDGPUOperand::Ptr defaultBoundCtrl() const; |
| AMDGPUOperand::Ptr defaultFI() const; |
| void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false); |
| void cvtDPP8(MCInst &Inst, const OperandVector &Operands) { cvtDPP(Inst, Operands, true); } |
| |
| OperandMatchResultTy parseSDWASel(OperandVector &Operands, StringRef Prefix, |
| AMDGPUOperand::ImmTy Type); |
| OperandMatchResultTy parseSDWADstUnused(OperandVector &Operands); |
| void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands); |
| void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands); |
| void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands); |
| void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands); |
| void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands); |
| void cvtSDWA(MCInst &Inst, const OperandVector &Operands, |
| uint64_t BasicInstType, |
| bool SkipDstVcc = false, |
| bool SkipSrcVcc = false); |
| |
| AMDGPUOperand::Ptr defaultBLGP() const; |
| AMDGPUOperand::Ptr defaultCBSZ() const; |
| AMDGPUOperand::Ptr defaultABID() const; |
| |
| OperandMatchResultTy parseEndpgmOp(OperandVector &Operands); |
| AMDGPUOperand::Ptr defaultEndpgmImmOperands() const; |
| }; |
| |
| struct OptionalOperand { |
| const char *Name; |
| AMDGPUOperand::ImmTy Type; |
| bool IsBit; |
| bool (*ConvertResult)(int64_t&); |
| }; |
| |
| } // end anonymous namespace |
| |
| // May be called with integer type with equivalent bitwidth. |
| static const fltSemantics *getFltSemantics(unsigned Size) { |
| switch (Size) { |
| case 4: |
| return &APFloat::IEEEsingle(); |
| case 8: |
| return &APFloat::IEEEdouble(); |
| case 2: |
| return &APFloat::IEEEhalf(); |
| default: |
| llvm_unreachable("unsupported fp type"); |
| } |
| } |
| |
| static const fltSemantics *getFltSemantics(MVT VT) { |
| return getFltSemantics(VT.getSizeInBits() / 8); |
| } |
| |
| static const fltSemantics *getOpFltSemantics(uint8_t OperandType) { |
| switch (OperandType) { |
| case AMDGPU::OPERAND_REG_IMM_INT32: |
| case AMDGPU::OPERAND_REG_IMM_FP32: |
| case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP32: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: |
| case AMDGPU::OPERAND_REG_IMM_V2FP32: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: |
| case AMDGPU::OPERAND_REG_IMM_V2INT32: |
| case AMDGPU::OPERAND_KIMM32: |
| return &APFloat::IEEEsingle(); |
| case AMDGPU::OPERAND_REG_IMM_INT64: |
| case AMDGPU::OPERAND_REG_IMM_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT64: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP64: |
| return &APFloat::IEEEdouble(); |
| case AMDGPU::OPERAND_REG_IMM_INT16: |
| case AMDGPU::OPERAND_REG_IMM_FP16: |
| case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: |
| case AMDGPU::OPERAND_REG_IMM_V2INT16: |
| case AMDGPU::OPERAND_REG_IMM_V2FP16: |
| case AMDGPU::OPERAND_KIMM16: |
| return &APFloat::IEEEhalf(); |
| default: |
| llvm_unreachable("unsupported fp type"); |
| } |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // Operand |
| //===----------------------------------------------------------------------===// |
| |
| static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) { |
| bool Lost; |
| |
| // Convert literal to single precision |
| APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT), |
| APFloat::rmNearestTiesToEven, |
| &Lost); |
| // We allow precision lost but not overflow or underflow |
| if (Status != APFloat::opOK && |
| Lost && |
| ((Status & APFloat::opOverflow) != 0 || |
| (Status & APFloat::opUnderflow) != 0)) { |
| return false; |
| } |
| |
| return true; |
| } |
| |
| static bool isSafeTruncation(int64_t Val, unsigned Size) { |
| return isUIntN(Size, Val) || isIntN(Size, Val); |
| } |
| |
| static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) { |
| if (VT.getScalarType() == MVT::i16) { |
| // FP immediate values are broken. |
| return isInlinableIntLiteral(Val); |
| } |
| |
| // f16/v2f16 operands work correctly for all values. |
| return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi); |
| } |
| |
| bool AMDGPUOperand::isInlinableImm(MVT type) const { |
| |
| // This is a hack to enable named inline values like |
| // shared_base with both 32-bit and 64-bit operands. |
| // Note that these values are defined as |
| // 32-bit operands only. |
| if (isInlineValue()) { |
| return true; |
| } |
| |
| if (!isImmTy(ImmTyNone)) { |
| // Only plain immediates are inlinable (e.g. "clamp" attribute is not) |
| return false; |
| } |
| // TODO: We should avoid using host float here. It would be better to |
| // check the float bit values which is what a few other places do. |
| // We've had bot failures before due to weird NaN support on mips hosts. |
| |
| APInt Literal(64, Imm.Val); |
| |
| if (Imm.IsFPImm) { // We got fp literal token |
| if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand |
| return AMDGPU::isInlinableLiteral64(Imm.Val, |
| AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val)); |
| if (!canLosslesslyConvertToFPType(FPLiteral, type)) |
| return false; |
| |
| if (type.getScalarSizeInBits() == 16) { |
| return isInlineableLiteralOp16( |
| static_cast<int16_t>(FPLiteral.bitcastToAPInt().getZExtValue()), |
| type, AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| // Check if single precision literal is inlinable |
| return AMDGPU::isInlinableLiteral32( |
| static_cast<int32_t>(FPLiteral.bitcastToAPInt().getZExtValue()), |
| AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| // We got int literal token. |
| if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand |
| return AMDGPU::isInlinableLiteral64(Imm.Val, |
| AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) { |
| return false; |
| } |
| |
| if (type.getScalarSizeInBits() == 16) { |
| return isInlineableLiteralOp16( |
| static_cast<int16_t>(Literal.getLoBits(16).getSExtValue()), |
| type, AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| return AMDGPU::isInlinableLiteral32( |
| static_cast<int32_t>(Literal.getLoBits(32).getZExtValue()), |
| AsmParser->hasInv2PiInlineImm()); |
| } |
| |
| bool AMDGPUOperand::isLiteralImm(MVT type) const { |
| // Check that this immediate can be added as literal |
| if (!isImmTy(ImmTyNone)) { |
| return false; |
| } |
| |
| if (!Imm.IsFPImm) { |
| // We got int literal token. |
| |
| if (type == MVT::f64 && hasFPModifiers()) { |
| // Cannot apply fp modifiers to int literals preserving the same semantics |
| // for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity, |
| // disable these cases. |
| return false; |
| } |
| |
| unsigned Size = type.getSizeInBits(); |
| if (Size == 64) |
| Size = 32; |
| |
| // FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP |
| // types. |
| return isSafeTruncation(Imm.Val, Size); |
| } |
| |
| // We got fp literal token |
| if (type == MVT::f64) { // Expected 64-bit fp operand |
| // We would set low 64-bits of literal to zeroes but we accept this literals |
| return true; |
| } |
| |
| if (type == MVT::i64) { // Expected 64-bit int operand |
| // We don't allow fp literals in 64-bit integer instructions. It is |
| // unclear how we should encode them. |
| return false; |
| } |
| |
| // We allow fp literals with f16x2 operands assuming that the specified |
| // literal goes into the lower half and the upper half is zero. We also |
| // require that the literal may be losslesly converted to f16. |
| MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 : |
| (type == MVT::v2i16)? MVT::i16 : |
| (type == MVT::v2f32)? MVT::f32 : type; |
| |
| APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val)); |
| return canLosslesslyConvertToFPType(FPLiteral, ExpectedType); |
| } |
| |
| bool AMDGPUOperand::isRegClass(unsigned RCID) const { |
| return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg()); |
| } |
| |
| bool AMDGPUOperand::isVRegWithInputMods() const { |
| return isRegClass(AMDGPU::VGPR_32RegClassID) || |
| // GFX90A allows DPP on 64-bit operands. |
| (isRegClass(AMDGPU::VReg_64RegClassID) && |
| AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]); |
| } |
| |
| bool AMDGPUOperand::isSDWAOperand(MVT type) const { |
| if (AsmParser->isVI()) |
| return isVReg32(); |
| else if (AsmParser->isGFX9Plus()) |
| return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type); |
| else |
| return false; |
| } |
| |
| bool AMDGPUOperand::isSDWAFP16Operand() const { |
| return isSDWAOperand(MVT::f16); |
| } |
| |
| bool AMDGPUOperand::isSDWAFP32Operand() const { |
| return isSDWAOperand(MVT::f32); |
| } |
| |
| bool AMDGPUOperand::isSDWAInt16Operand() const { |
| return isSDWAOperand(MVT::i16); |
| } |
| |
| bool AMDGPUOperand::isSDWAInt32Operand() const { |
| return isSDWAOperand(MVT::i32); |
| } |
| |
| bool AMDGPUOperand::isBoolReg() const { |
| auto FB = AsmParser->getFeatureBits(); |
| return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) || |
| (FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32())); |
| } |
| |
| uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const |
| { |
| assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers()); |
| assert(Size == 2 || Size == 4 || Size == 8); |
| |
| const uint64_t FpSignMask = (1ULL << (Size * 8 - 1)); |
| |
| if (Imm.Mods.Abs) { |
| Val &= ~FpSignMask; |
| } |
| if (Imm.Mods.Neg) { |
| Val ^= FpSignMask; |
| } |
| |
| return Val; |
| } |
| |
| void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const { |
| if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()), |
| Inst.getNumOperands())) { |
| addLiteralImmOperand(Inst, Imm.Val, |
| ApplyModifiers & |
| isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers()); |
| } else { |
| assert(!isImmTy(ImmTyNone) || !hasModifiers()); |
| Inst.addOperand(MCOperand::createImm(Imm.Val)); |
| setImmKindNone(); |
| } |
| } |
| |
| void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const { |
| const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); |
| auto OpNum = Inst.getNumOperands(); |
| // Check that this operand accepts literals |
| assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); |
| |
| if (ApplyModifiers) { |
| assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); |
| const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); |
| Val = applyInputFPModifiers(Val, Size); |
| } |
| |
| APInt Literal(64, Val); |
| uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType; |
| |
| if (Imm.IsFPImm) { // We got fp literal token |
| switch (OpTy) { |
| case AMDGPU::OPERAND_REG_IMM_INT64: |
| case AMDGPU::OPERAND_REG_IMM_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT64: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP64: |
| if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(), |
| AsmParser->hasInv2PiInlineImm())) { |
| Inst.addOperand(MCOperand::createImm(Literal.getZExtValue())); |
| setImmKindConst(); |
| return; |
| } |
| |
| // Non-inlineable |
| if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand |
| // For fp operands we check if low 32 bits are zeros |
| if (Literal.getLoBits(32) != 0) { |
| const_cast<AMDGPUAsmParser *>(AsmParser)->Warning(Inst.getLoc(), |
| "Can't encode literal as exact 64-bit floating-point operand. " |
| "Low 32-bits will be set to zero"); |
| } |
| |
| Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue())); |
| setImmKindLiteral(); |
| return; |
| } |
| |
| // We don't allow fp literals in 64-bit integer instructions. It is |
| // unclear how we should encode them. This case should be checked earlier |
| // in predicate methods (isLiteralImm()) |
| llvm_unreachable("fp literal in 64-bit integer instruction."); |
| |
| case AMDGPU::OPERAND_REG_IMM_INT32: |
| case AMDGPU::OPERAND_REG_IMM_FP32: |
| case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP32: |
| case AMDGPU::OPERAND_REG_IMM_INT16: |
| case AMDGPU::OPERAND_REG_IMM_FP16: |
| case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: |
| case AMDGPU::OPERAND_REG_IMM_V2INT16: |
| case AMDGPU::OPERAND_REG_IMM_V2FP16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: |
| case AMDGPU::OPERAND_REG_IMM_V2FP32: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: |
| case AMDGPU::OPERAND_REG_IMM_V2INT32: |
| case AMDGPU::OPERAND_KIMM32: |
| case AMDGPU::OPERAND_KIMM16: { |
| bool lost; |
| APFloat FPLiteral(APFloat::IEEEdouble(), Literal); |
| // Convert literal to single precision |
| FPLiteral.convert(*getOpFltSemantics(OpTy), |
| APFloat::rmNearestTiesToEven, &lost); |
| // We allow precision lost but not overflow or underflow. This should be |
| // checked earlier in isLiteralImm() |
| |
| uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue(); |
| Inst.addOperand(MCOperand::createImm(ImmVal)); |
| setImmKindLiteral(); |
| return; |
| } |
| default: |
| llvm_unreachable("invalid operand size"); |
| } |
| |
| return; |
| } |
| |
| // We got int literal token. |
| // Only sign extend inline immediates. |
| switch (OpTy) { |
| case AMDGPU::OPERAND_REG_IMM_INT32: |
| case AMDGPU::OPERAND_REG_IMM_FP32: |
| case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT32: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP32: |
| case AMDGPU::OPERAND_REG_IMM_V2INT16: |
| case AMDGPU::OPERAND_REG_IMM_V2FP16: |
| case AMDGPU::OPERAND_REG_IMM_V2FP32: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP32: |
| case AMDGPU::OPERAND_REG_IMM_V2INT32: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT32: |
| if (isSafeTruncation(Val, 32) && |
| AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val), |
| AsmParser->hasInv2PiInlineImm())) { |
| Inst.addOperand(MCOperand::createImm(Val)); |
| setImmKindConst(); |
| return; |
| } |
| |
| Inst.addOperand(MCOperand::createImm(Val & 0xffffffff)); |
| setImmKindLiteral(); |
| return; |
| |
| case AMDGPU::OPERAND_REG_IMM_INT64: |
| case AMDGPU::OPERAND_REG_IMM_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT64: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP64: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP64: |
| if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) { |
| Inst.addOperand(MCOperand::createImm(Val)); |
| setImmKindConst(); |
| return; |
| } |
| |
| Inst.addOperand(MCOperand::createImm(Lo_32(Val))); |
| setImmKindLiteral(); |
| return; |
| |
| case AMDGPU::OPERAND_REG_IMM_INT16: |
| case AMDGPU::OPERAND_REG_IMM_FP16: |
| case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: |
| case AMDGPU::OPERAND_REG_INLINE_C_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_FP16: |
| if (isSafeTruncation(Val, 16) && |
| AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), |
| AsmParser->hasInv2PiInlineImm())) { |
| Inst.addOperand(MCOperand::createImm(Val)); |
| setImmKindConst(); |
| return; |
| } |
| |
| Inst.addOperand(MCOperand::createImm(Val & 0xffff)); |
| setImmKindLiteral(); |
| return; |
| |
| case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: |
| case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: { |
| assert(isSafeTruncation(Val, 16)); |
| assert(AMDGPU::isInlinableLiteral16(static_cast<int16_t>(Val), |
| AsmParser->hasInv2PiInlineImm())); |
| |
| Inst.addOperand(MCOperand::createImm(Val)); |
| return; |
| } |
| case AMDGPU::OPERAND_KIMM32: |
| Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue())); |
| setImmKindNone(); |
| return; |
| case AMDGPU::OPERAND_KIMM16: |
| Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue())); |
| setImmKindNone(); |
| return; |
| default: |
| llvm_unreachable("invalid operand size"); |
| } |
| } |
| |
| template <unsigned Bitwidth> |
| void AMDGPUOperand::addKImmFPOperands(MCInst &Inst, unsigned N) const { |
| APInt Literal(64, Imm.Val); |
| setImmKindNone(); |
| |
| if (!Imm.IsFPImm) { |
| // We got int literal token. |
| Inst.addOperand(MCOperand::createImm(Literal.getLoBits(Bitwidth).getZExtValue())); |
| return; |
| } |
| |
| bool Lost; |
| APFloat FPLiteral(APFloat::IEEEdouble(), Literal); |
| FPLiteral.convert(*getFltSemantics(Bitwidth / 8), |
| APFloat::rmNearestTiesToEven, &Lost); |
| Inst.addOperand(MCOperand::createImm(FPLiteral.bitcastToAPInt().getZExtValue())); |
| } |
| |
| void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const { |
| Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI()))); |
| } |
| |
| static bool isInlineValue(unsigned Reg) { |
| switch (Reg) { |
| case AMDGPU::SRC_SHARED_BASE: |
| case AMDGPU::SRC_SHARED_LIMIT: |
| case AMDGPU::SRC_PRIVATE_BASE: |
| case AMDGPU::SRC_PRIVATE_LIMIT: |
| case AMDGPU::SRC_POPS_EXITING_WAVE_ID: |
| return true; |
| case AMDGPU::SRC_VCCZ: |
| case AMDGPU::SRC_EXECZ: |
| case AMDGPU::SRC_SCC: |
| return true; |
| case AMDGPU::SGPR_NULL: |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| bool AMDGPUOperand::isInlineValue() const { |
| return isRegKind() && ::isInlineValue(getReg()); |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // AsmParser |
| //===----------------------------------------------------------------------===// |
| |
| static int getRegClass(RegisterKind Is, unsigned RegWidth) { |
| if (Is == IS_VGPR) { |
| switch (RegWidth) { |
| default: return -1; |
| case 1: return AMDGPU::VGPR_32RegClassID; |
| case 2: return AMDGPU::VReg_64RegClassID; |
| case 3: return AMDGPU::VReg_96RegClassID; |
| case 4: return AMDGPU::VReg_128RegClassID; |
| case 5: return AMDGPU::VReg_160RegClassID; |
| case 6: return AMDGPU::VReg_192RegClassID; |
| case 7: return AMDGPU::VReg_224RegClassID; |
| case 8: return AMDGPU::VReg_256RegClassID; |
| case 16: return AMDGPU::VReg_512RegClassID; |
| case 32: return AMDGPU::VReg_1024RegClassID; |
| } |
| } else if (Is == IS_TTMP) { |
| switch (RegWidth) { |
| default: return -1; |
| case 1: return AMDGPU::TTMP_32RegClassID; |
| case 2: return AMDGPU::TTMP_64RegClassID; |
| case 4: return AMDGPU::TTMP_128RegClassID; |
| case 8: return AMDGPU::TTMP_256RegClassID; |
| case 16: return AMDGPU::TTMP_512RegClassID; |
| } |
| } else if (Is == IS_SGPR) { |
| switch (RegWidth) { |
| default: return -1; |
| case 1: return AMDGPU::SGPR_32RegClassID; |
| case 2: return AMDGPU::SGPR_64RegClassID; |
| case 3: return AMDGPU::SGPR_96RegClassID; |
| case 4: return AMDGPU::SGPR_128RegClassID; |
| case 5: return AMDGPU::SGPR_160RegClassID; |
| case 6: return AMDGPU::SGPR_192RegClassID; |
| case 7: return AMDGPU::SGPR_224RegClassID; |
| case 8: return AMDGPU::SGPR_256RegClassID; |
| case 16: return AMDGPU::SGPR_512RegClassID; |
| } |
| } else if (Is == IS_AGPR) { |
| switch (RegWidth) { |
| default: return -1; |
| case 1: return AMDGPU::AGPR_32RegClassID; |
| case 2: return AMDGPU::AReg_64RegClassID; |
| case 3: return AMDGPU::AReg_96RegClassID; |
| case 4: return AMDGPU::AReg_128RegClassID; |
| case 5: return AMDGPU::AReg_160RegClassID; |
| case 6: return AMDGPU::AReg_192RegClassID; |
| case 7: return AMDGPU::AReg_224RegClassID; |
| case 8: return AMDGPU::AReg_256RegClassID; |
| case 16: return AMDGPU::AReg_512RegClassID; |
| case 32: return AMDGPU::AReg_1024RegClassID; |
| } |
| } |
| return -1; |
| } |
| |
| static unsigned getSpecialRegForName(StringRef RegName) { |
| return StringSwitch<unsigned>(RegName) |
| .Case("exec", AMDGPU::EXEC) |
| .Case("vcc", AMDGPU::VCC) |
| .Case("flat_scratch", AMDGPU::FLAT_SCR) |
| .Case("xnack_mask", AMDGPU::XNACK_MASK) |
| .Case("shared_base", AMDGPU::SRC_SHARED_BASE) |
| .Case("src_shared_base", AMDGPU::SRC_SHARED_BASE) |
| .Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT) |
| .Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT) |
| .Case("private_base", AMDGPU::SRC_PRIVATE_BASE) |
| .Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE) |
| .Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT) |
| .Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT) |
| .Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) |
| .Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID) |
| .Case("lds_direct", AMDGPU::LDS_DIRECT) |
| .Case("src_lds_direct", AMDGPU::LDS_DIRECT) |
| .Case("m0", AMDGPU::M0) |
| .Case("vccz", AMDGPU::SRC_VCCZ) |
| .Case("src_vccz", AMDGPU::SRC_VCCZ) |
| .Case("execz", AMDGPU::SRC_EXECZ) |
| .Case("src_execz", AMDGPU::SRC_EXECZ) |
| .Case("scc", AMDGPU::SRC_SCC) |
| .Case("src_scc", AMDGPU::SRC_SCC) |
| .Case("tba", AMDGPU::TBA) |
| .Case("tma", AMDGPU::TMA) |
| .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO) |
| .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI) |
| .Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO) |
| .Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI) |
| .Case("vcc_lo", AMDGPU::VCC_LO) |
| .Case("vcc_hi", AMDGPU::VCC_HI) |
| .Case("exec_lo", AMDGPU::EXEC_LO) |
| .Case("exec_hi", AMDGPU::EXEC_HI) |
| .Case("tma_lo", AMDGPU::TMA_LO) |
| .Case("tma_hi", AMDGPU::TMA_HI) |
| .Case("tba_lo", AMDGPU::TBA_LO) |
| .Case("tba_hi", AMDGPU::TBA_HI) |
| .Case("pc", AMDGPU::PC_REG) |
| .Case("null", AMDGPU::SGPR_NULL) |
| .Default(AMDGPU::NoRegister); |
| } |
| |
| bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, |
| SMLoc &EndLoc, bool RestoreOnFailure) { |
| auto R = parseRegister(); |
| if (!R) return true; |
| assert(R->isReg()); |
| RegNo = R->getReg(); |
| StartLoc = R->getStartLoc(); |
| EndLoc = R->getEndLoc(); |
| return false; |
| } |
| |
| bool AMDGPUAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, |
| SMLoc &EndLoc) { |
| return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); |
| } |
| |
| OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(unsigned &RegNo, |
| SMLoc &StartLoc, |
| SMLoc &EndLoc) { |
| bool Result = |
| ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); |
| bool PendingErrors = getParser().hasPendingError(); |
| getParser().clearPendingErrors(); |
| if (PendingErrors) |
| return MatchOperand_ParseFail; |
| if (Result) |
| return MatchOperand_NoMatch; |
| return MatchOperand_Success; |
| } |
| |
| bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, |
| RegisterKind RegKind, unsigned Reg1, |
| SMLoc Loc) { |
| switch (RegKind) { |
| case IS_SPECIAL: |
| if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) { |
| Reg = AMDGPU::EXEC; |
| RegWidth = 2; |
| return true; |
| } |
| if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) { |
| Reg = AMDGPU::FLAT_SCR; |
| RegWidth = 2; |
| return true; |
| } |
| if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) { |
| Reg = AMDGPU::XNACK_MASK; |
| RegWidth = 2; |
| return true; |
| } |
| if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) { |
| Reg = AMDGPU::VCC; |
| RegWidth = 2; |
| return true; |
| } |
| if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) { |
| Reg = AMDGPU::TBA; |
| RegWidth = 2; |
| return true; |
| } |
| if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) { |
| Reg = AMDGPU::TMA; |
| RegWidth = 2; |
| return true; |
| } |
| Error(Loc, "register does not fit in the list"); |
| return false; |
| case IS_VGPR: |
| case IS_SGPR: |
| case IS_AGPR: |
| case IS_TTMP: |
| if (Reg1 != Reg + RegWidth) { |
| Error(Loc, "registers in a list must have consecutive indices"); |
| return false; |
| } |
| RegWidth++; |
| return true; |
| default: |
| llvm_unreachable("unexpected register kind"); |
| } |
| } |
| |
| struct RegInfo { |
| StringLiteral Name; |
| RegisterKind Kind; |
| }; |
| |
| static constexpr RegInfo RegularRegisters[] = { |
| {{"v"}, IS_VGPR}, |
| {{"s"}, IS_SGPR}, |
| {{"ttmp"}, IS_TTMP}, |
| {{"acc"}, IS_AGPR}, |
| {{"a"}, IS_AGPR}, |
| }; |
| |
| static bool isRegularReg(RegisterKind Kind) { |
| return Kind == IS_VGPR || |
| Kind == IS_SGPR || |
| Kind == IS_TTMP || |
| Kind == IS_AGPR; |
| } |
| |
| static const RegInfo* getRegularRegInfo(StringRef Str) { |
| for (const RegInfo &Reg : RegularRegisters) |
| if (Str.startswith(Reg.Name)) |
| return &Reg; |
| return nullptr; |
| } |
| |
| static bool getRegNum(StringRef Str, unsigned& Num) { |
| return !Str.getAsInteger(10, Num); |
| } |
| |
| bool |
| AMDGPUAsmParser::isRegister(const AsmToken &Token, |
| const AsmToken &NextToken) const { |
| |
| // A list of consecutive registers: [s0,s1,s2,s3] |
| if (Token.is(AsmToken::LBrac)) |
| return true; |
| |
| if (!Token.is(AsmToken::Identifier)) |
| return false; |
| |
| // A single register like s0 or a range of registers like s[0:1] |
| |
| StringRef Str = Token.getString(); |
| const RegInfo *Reg = getRegularRegInfo(Str); |
| if (Reg) { |
| StringRef RegName = Reg->Name; |
| StringRef RegSuffix = Str.substr(RegName.size()); |
| if (!RegSuffix.empty()) { |
| unsigned Num; |
| // A single register with an index: rXX |
| if (getRegNum(RegSuffix, Num)) |
| return true; |
| } else { |
| // A range of registers: r[XX:YY]. |
| if (NextToken.is(AsmToken::LBrac)) |
| return true; |
| } |
| } |
| |
| return getSpecialRegForName(Str) != AMDGPU::NoRegister; |
| } |
| |
| bool |
| AMDGPUAsmParser::isRegister() |
| { |
| return isRegister(getToken(), peekToken()); |
| } |
| |
| unsigned |
| AMDGPUAsmParser::getRegularReg(RegisterKind RegKind, |
| unsigned RegNum, |
| unsigned RegWidth, |
| SMLoc Loc) { |
| |
| assert(isRegularReg(RegKind)); |
| |
| unsigned AlignSize = 1; |
| if (RegKind == IS_SGPR || RegKind == IS_TTMP) { |
| // SGPR and TTMP registers must be aligned. |
| // Max required alignment is 4 dwords. |
| AlignSize = std::min(RegWidth, 4u); |
| } |
| |
| if (RegNum % AlignSize != 0) { |
| Error(Loc, "invalid register alignment"); |
| return AMDGPU::NoRegister; |
| } |
| |
| unsigned RegIdx = RegNum / AlignSize; |
| int RCID = getRegClass(RegKind, RegWidth); |
| if (RCID == -1) { |
| Error(Loc, "invalid or unsupported register size"); |
| return AMDGPU::NoRegister; |
| } |
| |
| const MCRegisterInfo *TRI = getContext().getRegisterInfo(); |
| const MCRegisterClass RC = TRI->getRegClass(RCID); |
| if (RegIdx >= RC.getNumRegs()) { |
| Error(Loc, "register index is out of range"); |
| return AMDGPU::NoRegister; |
| } |
| |
| return RC.getRegister(RegIdx); |
| } |
| |
| bool |
| AMDGPUAsmParser::ParseRegRange(unsigned& Num, unsigned& Width) { |
| int64_t RegLo, RegHi; |
| if (!skipToken(AsmToken::LBrac, "missing register index")) |
| return false; |
| |
| SMLoc FirstIdxLoc = getLoc(); |
| SMLoc SecondIdxLoc; |
| |
| if (!parseExpr(RegLo)) |
| return false; |
| |
| if (trySkipToken(AsmToken::Colon)) { |
| SecondIdxLoc = getLoc(); |
| if (!parseExpr(RegHi)) |
| return false; |
| } else { |
| RegHi = RegLo; |
| } |
| |
| if (!skipToken(AsmToken::RBrac, "expected a closing square bracket")) |
| return false; |
| |
| if (!isUInt<32>(RegLo)) { |
| Error(FirstIdxLoc, "invalid register index"); |
| return false; |
| } |
| |
| if (!isUInt<32>(RegHi)) { |
| Error(SecondIdxLoc, "invalid register index"); |
| return false; |
| } |
| |
| if (RegLo > RegHi) { |
| Error(FirstIdxLoc, "first register index should not exceed second index"); |
| return false; |
| } |
| |
| Num = static_cast<unsigned>(RegLo); |
| Width = (RegHi - RegLo) + 1; |
| return true; |
| } |
| |
| unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind, |
| unsigned &RegNum, unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens) { |
| assert(isToken(AsmToken::Identifier)); |
| unsigned Reg = getSpecialRegForName(getTokenStr()); |
| if (Reg) { |
| RegNum = 0; |
| RegWidth = 1; |
| RegKind = IS_SPECIAL; |
| Tokens.push_back(getToken()); |
| lex(); // skip register name |
| } |
| return Reg; |
| } |
| |
| unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind, |
| unsigned &RegNum, unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens) { |
| assert(isToken(AsmToken::Identifier)); |
| StringRef RegName = getTokenStr(); |
| auto Loc = getLoc(); |
| |
| const RegInfo *RI = getRegularRegInfo(RegName); |
| if (!RI) { |
| Error(Loc, "invalid register name"); |
| return AMDGPU::NoRegister; |
| } |
| |
| Tokens.push_back(getToken()); |
| lex(); // skip register name |
| |
| RegKind = RI->Kind; |
| StringRef RegSuffix = RegName.substr(RI->Name.size()); |
| if (!RegSuffix.empty()) { |
| // Single 32-bit register: vXX. |
| if (!getRegNum(RegSuffix, RegNum)) { |
| Error(Loc, "invalid register index"); |
| return AMDGPU::NoRegister; |
| } |
| RegWidth = 1; |
| } else { |
| // Range of registers: v[XX:YY]. ":YY" is optional. |
| if (!ParseRegRange(RegNum, RegWidth)) |
| return AMDGPU::NoRegister; |
| } |
| |
| return getRegularReg(RegKind, RegNum, RegWidth, Loc); |
| } |
| |
| unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum, |
| unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens) { |
| unsigned Reg = AMDGPU::NoRegister; |
| auto ListLoc = getLoc(); |
| |
| if (!skipToken(AsmToken::LBrac, |
| "expected a register or a list of registers")) { |
| return AMDGPU::NoRegister; |
| } |
| |
| // List of consecutive registers, e.g.: [s0,s1,s2,s3] |
| |
| auto Loc = getLoc(); |
| if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) |
| return AMDGPU::NoRegister; |
| if (RegWidth != 1) { |
| Error(Loc, "expected a single 32-bit register"); |
| return AMDGPU::NoRegister; |
| } |
| |
| for (; trySkipToken(AsmToken::Comma); ) { |
| RegisterKind NextRegKind; |
| unsigned NextReg, NextRegNum, NextRegWidth; |
| Loc = getLoc(); |
| |
| if (!ParseAMDGPURegister(NextRegKind, NextReg, |
| NextRegNum, NextRegWidth, |
| Tokens)) { |
| return AMDGPU::NoRegister; |
| } |
| if (NextRegWidth != 1) { |
| Error(Loc, "expected a single 32-bit register"); |
| return AMDGPU::NoRegister; |
| } |
| if (NextRegKind != RegKind) { |
| Error(Loc, "registers in a list must be of the same kind"); |
| return AMDGPU::NoRegister; |
| } |
| if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc)) |
| return AMDGPU::NoRegister; |
| } |
| |
| if (!skipToken(AsmToken::RBrac, |
| "expected a comma or a closing square bracket")) { |
| return AMDGPU::NoRegister; |
| } |
| |
| if (isRegularReg(RegKind)) |
| Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc); |
| |
| return Reg; |
| } |
| |
| bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, |
| unsigned &RegNum, unsigned &RegWidth, |
| SmallVectorImpl<AsmToken> &Tokens) { |
| auto Loc = getLoc(); |
| Reg = AMDGPU::NoRegister; |
| |
| if (isToken(AsmToken::Identifier)) { |
| Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens); |
| if (Reg == AMDGPU::NoRegister) |
| Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens); |
| } else { |
| Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens); |
| } |
| |
| const MCRegisterInfo *TRI = getContext().getRegisterInfo(); |
| if (Reg == AMDGPU::NoRegister) { |
| assert(Parser.hasPendingError()); |
| return false; |
| } |
| |
| if (!subtargetHasRegister(*TRI, Reg)) { |
| if (Reg == AMDGPU::SGPR_NULL) { |
| Error(Loc, "'null' operand is not supported on this GPU"); |
| } else { |
| Error(Loc, "register not available on this GPU"); |
| } |
| return false; |
| } |
| |
| return true; |
| } |
| |
| bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg, |
| unsigned &RegNum, unsigned &RegWidth, |
| bool RestoreOnFailure /*=false*/) { |
| Reg = AMDGPU::NoRegister; |
| |
| SmallVector<AsmToken, 1> Tokens; |
| if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) { |
| if (RestoreOnFailure) { |
| while (!Tokens.empty()) { |
| getLexer().UnLex(Tokens.pop_back_val()); |
| } |
| } |
| return true; |
| } |
| return false; |
| } |
| |
| Optional<StringRef> |
|
