[CodeGen] Rename functions PrintReg* to printReg*
LLVM Coding Standards:
Function names should be verb phrases (as they represent actions), and
command-like function should be imperative. The name should be camel
case, and start with a lower case letter (e.g. openFile() or isFoo()).
Differential Revision: https://reviews.llvm.org/D40416
llvm-svn: 319168
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 39b567b..5e20d8c 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -182,7 +182,7 @@
void BitTracker::print_cells(raw_ostream &OS) const {
for (const std::pair<unsigned, RegisterCell> P : Map)
- dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
+ dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n";
}
BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F)
@@ -794,14 +794,14 @@
RegisterRef RU = PI.getOperand(i);
RegisterCell ResC = ME.getCell(RU, Map);
if (Trace)
- dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+ dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ResC << "\n";
Changed |= DefC.meet(ResC, DefRR.Reg);
}
if (Changed) {
if (Trace)
- dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
+ dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub)
<< " cell: " << DefC << "\n";
ME.putCell(DefRR, DefC, Map);
visitUsesOf(DefRR.Reg);
@@ -826,13 +826,13 @@
if (!MO.isReg() || !MO.isUse())
continue;
RegisterRef RU(MO);
- dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub)
+ dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub)
<< " cell: " << ME.getCell(RU, Map) << "\n";
}
dbgs() << "Outputs:\n";
for (const std::pair<unsigned, RegisterCell> &P : ResMap) {
RegisterRef RD(P.first);
- dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: "
+ dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: "
<< ME.getCell(RD, ResMap) << "\n";
}
}
@@ -949,7 +949,7 @@
void BT::visitUsesOf(unsigned Reg) {
if (Trace)
- dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n";
+ dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n";
for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) {
if (!InstrExec.count(&UseI))
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index a1f9e81..cbf1b0d 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -173,7 +173,7 @@
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
- OS << ' ' << PrintReg(R, P.TRI);
+ OS << ' ' << printReg(R, P.TRI);
OS << " }";
return OS;
}
@@ -2453,7 +2453,7 @@
return false;
DEBUG({
- dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub)
+ dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub)
<< ", MI: " << *MI;
dbgs() << "Cell: " << RC << '\n';
dbgs() << "Expected bitfield size: " << Len << " bits, "
@@ -3004,9 +3004,9 @@
DEBUG({
dbgs() << "Phis: {";
for (auto &I : Phis) {
- dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi("
- << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
- << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
+ dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi("
+ << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
+ << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
<< I.LB->getNumber() << ')';
}
dbgs() << " }\n";
@@ -3126,8 +3126,8 @@
for (unsigned i = 0, n = Groups.size(); i < n; ++i) {
InstrGroup &G = Groups[i];
dbgs() << "Group[" << i << "] inp: "
- << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
- << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
+ << printReg(G.Inp.Reg, HRI, G.Inp.Sub)
+ << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";
for (unsigned j = 0, m = G.Ins.size(); j < m; ++j)
dbgs() << " " << *G.Ins[j];
}
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 6d30191..8297c47 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -104,7 +104,7 @@
break;
}
#ifndef NDEBUG
- dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class "
+ dbgs() << printReg(Reg, &TRI, Sub) << " in reg class "
<< TRI.getRegClassName(&RC) << '\n';
#endif
llvm_unreachable("Unexpected register/subregister");
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index a63ab8f..00db408 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -531,7 +531,7 @@
const HexagonBlockRanges::PrintRangeMap &P) {
for (auto &I : P.Map) {
const HexagonBlockRanges::RangeList &RL = I.second;
- OS << PrintReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
+ OS << printReg(I.first.Reg, &P.TRI, I.first.Sub) << " -> " << RL << "\n";
}
return OS;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index 2235927..1e55c4b 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -422,7 +422,7 @@
LLVM_ATTRIBUTE_UNUSED
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &P) {
if (P.Rs.Reg != 0)
- OS << PrintReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
+ OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub);
else
OS << "noreg";
return OS;
@@ -439,7 +439,7 @@
raw_ostream &operator<< (raw_ostream &OS, const PrintExpr &P) {
OS << "## " << (P.Ex.Neg ? "- " : "+ ");
if (P.Ex.Rs.Reg != 0)
- OS << PrintReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
+ OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub);
else
OS << "__";
OS << " << " << P.Ex.S;
@@ -468,7 +468,7 @@
const auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo();
OS << "bb#" << MBB.getNumber() << ": ";
if (ED.Rd.Reg != 0)
- OS << PrintReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
+ OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub);
else
OS << "__";
OS << " = " << PrintExpr(ED.Expr, HRI);
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 7462b59..ed6c40d 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -88,7 +88,7 @@
: Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
void print(const TargetRegisterInfo *TRI = nullptr) const {
- dbgs() << PrintReg(Reg, TRI, SubReg);
+ dbgs() << printReg(Reg, TRI, SubReg);
}
bool operator== (const Register &R) const {
@@ -610,7 +610,7 @@
void MachineConstPropagator::CellMap::print(raw_ostream &os,
const TargetRegisterInfo &TRI) const {
for (auto &I : Map)
- dbgs() << " " << PrintReg(I.first, &TRI) << " -> " << I.second << '\n';
+ dbgs() << " " << printReg(I.first, &TRI) << " -> " << I.second << '\n';
}
#endif
@@ -659,7 +659,7 @@
LatticeCell SrcC;
bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
DEBUG(dbgs() << " edge from BB#" << PBN << ": "
- << PrintReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
+ << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
<< SrcC << '\n');
Changed |= Eval ? DefC.meet(SrcC)
: DefC.setBottom();
@@ -778,7 +778,7 @@
}
void MachineConstPropagator::visitUsesOf(unsigned Reg) {
- DEBUG(dbgs() << "Visiting uses of " << PrintReg(Reg, &MCE.TRI)
+ DEBUG(dbgs() << "Visiting uses of " << printReg(Reg, &MCE.TRI)
<< Cells.get(Reg) << '\n');
for (MachineInstr &MI : MRI->use_nodbg_instructions(Reg)) {
// Do not process non-executable instructions. They can become exceutable
@@ -2788,7 +2788,7 @@
HasUse = true;
// PHIs can legitimately have "top" cells after propagation.
if (!MI.isPHI() && !Inputs.has(R.Reg)) {
- dbgs() << "Top " << PrintReg(R.Reg, &HRI, R.SubReg)
+ dbgs() << "Top " << printReg(R.Reg, &HRI, R.SubReg)
<< " in MI: " << MI;
continue;
}
@@ -2804,7 +2804,7 @@
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue;
unsigned R = MO.getReg();
- dbgs() << PrintReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
+ dbgs() << printReg(R, &TRI) << ": " << Inputs.get(R) << "\n";
}
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 2d9bd00..bec759a 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -144,7 +144,7 @@
const PrintFP &P) LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<<(raw_ostream &OS, const PrintFP &P) {
OS << "{ SplitB:" << PrintMB(P.FP.SplitB)
- << ", PredR:" << PrintReg(P.FP.PredR, &P.TRI)
+ << ", PredR:" << printReg(P.FP.PredR, &P.TRI)
<< ", TrueB:" << PrintMB(P.FP.TrueB)
<< ", FalseB:" << PrintMB(P.FP.FalseB)
<< ", JoinB:" << PrintMB(P.FP.JoinB) << " }";
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 66cfab9..51c3b78 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -1137,8 +1137,8 @@
DEBUG(dbgs() << "compatible registers: ("
<< (Overlap ? "overlap" : "disjoint") << ")\n "
- << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
- << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
+ << printReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
+ << printReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
if (R1.Sub || R2.Sub)
return false;
if (Overlap)
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index e13bbac..ebb7add 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -1371,7 +1371,7 @@
dbgs() << '{';
for (int x = Regs.find_first(); x >= 0; x = Regs.find_next(x)) {
unsigned R = x;
- dbgs() << ' ' << PrintReg(R, &TRI);
+ dbgs() << ' ' << printReg(R, &TRI);
}
dbgs() << " }";
}
@@ -1393,7 +1393,7 @@
DEBUG(dbgs() << "Initial CS registers: {");
for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
unsigned R = CSI[i].getReg();
- DEBUG(dbgs() << ' ' << PrintReg(R, TRI));
+ DEBUG(dbgs() << ' ' << printReg(R, TRI));
for (MCSubRegIterator SR(R, TRI, true); SR.isValid(); ++SR)
SRegs[*SR] = true;
}
@@ -1490,7 +1490,7 @@
for (unsigned i = 0, n = CSI.size(); i < n; ++i) {
int FI = CSI[i].getFrameIdx();
int Off = MFI.getObjectOffset(FI);
- dbgs() << ' ' << PrintReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
+ dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
if (Off >= 0)
dbgs() << '+';
dbgs() << Off;
@@ -1503,7 +1503,7 @@
bool MissedReg = false;
for (int x = SRegs.find_first(); x >= 0; x = SRegs.find_next(x)) {
unsigned R = x;
- dbgs() << PrintReg(R, TRI) << ' ';
+ dbgs() << printReg(R, TRI) << ' ';
MissedReg = true;
}
if (MissedReg)
@@ -2207,7 +2207,7 @@
auto *RC = HII.getRegClass(SI.getDesc(), 2, &HRI, MF);
// The this-> is needed to unconfuse MSVC.
unsigned FoundR = this->findPhysReg(MF, Range, IM, DM, RC);
- DEBUG(dbgs() << "Replacement reg:" << PrintReg(FoundR, &HRI) << '\n');
+ DEBUG(dbgs() << "Replacement reg:" << printReg(FoundR, &HRI) << '\n');
if (FoundR == 0)
continue;
#ifndef NDEBUG
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 46d039a..09d3e6d 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -180,7 +180,7 @@
raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) {
OS << '{';
for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R))
- OS << ' ' << PrintReg(R, P.TRI);
+ OS << ' ' << printReg(R, P.TRI);
OS << " }";
return OS;
}
@@ -419,7 +419,7 @@
for (OrderedRegisterList::const_iterator I = B; I != E; ++I) {
if (I != B)
OS << ", ";
- OS << PrintReg(*I, P.TRI);
+ OS << printReg(*I, P.TRI);
}
OS << ')';
return OS;
@@ -467,7 +467,7 @@
raw_ostream &operator<< (raw_ostream &OS, const PrintIFR &P) {
unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR;
- OS << '(' << PrintReg(SrcR, P.TRI) << ',' << PrintReg(InsR, P.TRI)
+ OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI)
<< ",#" << P.IFR.Wdh << ",#" << P.IFR.Off << ')';
return OS;
}
@@ -568,7 +568,7 @@
using iterator = IFMapType::const_iterator;
for (iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- dbgs() << " " << PrintReg(I->first, HRI) << ":\n";
+ dbgs() << " " << printReg(I->first, HRI) << ":\n";
const IFListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i)
dbgs() << " " << PrintIFR(LL[i].first, HRI) << ", "
@@ -781,7 +781,7 @@
bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
OrderedRegisterList &AVs) {
if (isDebug()) {
- dbgs() << __func__ << ": " << PrintReg(VR, HRI)
+ dbgs() << __func__ << ": " << printReg(VR, HRI)
<< " AVs: " << PrintORL(AVs, HRI) << "\n";
}
if (AVs.size() == 0)
@@ -846,12 +846,12 @@
}
if (isDebug()) {
- dbgs() << "Prefixes matching register " << PrintReg(VR, HRI) << "\n";
+ dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n";
for (LRSMapType::iterator I = LM.begin(), E = LM.end(); I != E; ++I) {
dbgs() << " L=" << I->first << ':';
const RSListType &LL = I->second;
for (unsigned i = 0, n = LL.size(); i < n; ++i)
- dbgs() << " (" << PrintReg(LL[i].first, HRI) << ",@"
+ dbgs() << " (" << printReg(LL[i].first, HRI) << ",@"
<< LL[i].second << ')';
dbgs() << '\n';
}
@@ -898,8 +898,8 @@
if (!isValidInsertForm(VR, SrcR, InsR, L, S))
continue;
if (isDebug()) {
- dbgs() << PrintReg(VR, HRI) << " = insert(" << PrintReg(SrcR, HRI)
- << ',' << PrintReg(InsR, HRI) << ",#" << L << ",#"
+ dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI)
+ << ',' << printReg(InsR, HRI) << ",#" << L << ",#"
<< S << ")\n";
}
IFRecordWithRegSet RR(IFRecord(SrcR, InsR, L, S), RegisterSet());
@@ -1524,7 +1524,7 @@
for (RegisterOrdering::iterator I = CellOrd.begin(), E = CellOrd.end();
I != E; ++I) {
unsigned VR = I->first, Pos = I->second;
- dbgs() << PrintReg(VR, HRI) << " -> " << Pos << "\n";
+ dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n";
}
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 8ba4658..4eb24e0 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -74,7 +74,7 @@
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
LLVM_ATTRIBUTE_UNUSED;
raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
- return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
+ return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
}
class HexagonGenPredicate : public MachineFunctionPass {
@@ -223,12 +223,12 @@
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
DEBUG(dbgs() << __func__ << ": "
- << PrintReg(Reg.R, TRI, Reg.S) << "\n");
+ << printReg(Reg.R, TRI, Reg.S) << "\n");
using use_iterator = MachineRegisterInfo::use_iterator;
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
if (I == E) {
- DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
+ DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n');
MachineInstr *DefI = MRI->getVRegDef(Reg.R);
DefI->eraseFromParent();
return;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 7250f48..5ca8b0f 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -357,7 +357,7 @@
}
void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
- if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
+ if (isReg()) { OS << printReg(Contents.R.Reg, TRI, Contents.R.Sub); }
if (isImm()) { OS << Contents.ImmVal; }
}
};
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 3a4ebe0..3c0b306 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -830,8 +830,8 @@
#ifndef NDEBUG
// Show the invalid registers to ease debugging.
dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
- << ": " << PrintReg(DestReg, &HRI)
- << " = " << PrintReg(SrcReg, &HRI) << '\n';
+ << ": " << printReg(DestReg, &HRI)
+ << " = " << printReg(SrcReg, &HRI) << '\n';
#endif
llvm_unreachable("Unimplemented");
}
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 1e908ab..75d6750 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -136,7 +136,7 @@
const USet &Part, const TargetRegisterInfo &TRI) {
dbgs() << '{';
for (auto I : Part)
- dbgs() << ' ' << PrintReg(I, &TRI);
+ dbgs() << ' ' << printReg(I, &TRI);
dbgs() << " }";
}
#endif
@@ -244,7 +244,7 @@
if (FixedRegs[x])
continue;
unsigned R = TargetRegisterInfo::index2VirtReg(x);
- DEBUG(dbgs() << PrintReg(R, TRI) << " ~~");
+ DEBUG(dbgs() << printReg(R, TRI) << " ~~");
USet &Asc = AssocMap[R];
for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
U != Z; ++U) {
@@ -267,7 +267,7 @@
unsigned u = TargetRegisterInfo::virtReg2Index(T);
if (FixedRegs[u])
continue;
- DEBUG(dbgs() << ' ' << PrintReg(T, TRI));
+ DEBUG(dbgs() << ' ' << printReg(T, TRI));
Asc.insert(T);
// Make it symmetric.
AssocMap[T].insert(R);
@@ -1122,8 +1122,8 @@
unsigned LoR = MRI->createVirtualRegister(IntRC);
unsigned HiR = MRI->createVirtualRegister(IntRC);
- DEBUG(dbgs() << "Created mapping: " << PrintReg(DR, TRI) << " -> "
- << PrintReg(HiR, TRI) << ':' << PrintReg(LoR, TRI) << '\n');
+ DEBUG(dbgs() << "Created mapping: " << printReg(DR, TRI) << " -> "
+ << printReg(HiR, TRI) << ':' << printReg(LoR, TRI) << '\n');
PairMap.insert(std::make_pair(DR, UUPair(LoR, HiR)));
}
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index fed5a66..740cd11 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -62,7 +62,7 @@
raw_ostream &operator<< (raw_ostream &OS, const Print<Liveness::RefMap> &P) {
OS << '{';
for (auto &I : P.Obj) {
- OS << ' ' << PrintReg(I.first, &P.G.getTRI()) << '{';
+ OS << ' ' << printReg(I.first, &P.G.getTRI()) << '{';
for (auto J = I.second.begin(), E = I.second.end(); J != E; ) {
OS << Print<NodeId>(J->first, P.G) << PrintLaneMaskOpt(J->second);
if (++J != E)
diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
index 429add9..9408c5d 100644
--- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
@@ -365,7 +365,7 @@
void RegisterAggr::print(raw_ostream &OS) const {
OS << '{';
for (int U = Units.find_first(); U >= 0; U = Units.find_next(U))
- OS << ' ' << PrintRegUnit(U, &PRI.getTRI());
+ OS << ' ' << printRegUnit(U, &PRI.getTRI());
OS << " }";
}
