# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
--- |
  target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64"

  define i32 @load_store_test(i24* %ptr, i24* %ptr2) {
    %val = load i24, i24* %ptr
    store i24 %val, i24* %ptr2
    ret i32 0
  }

...
---
name:            load_store_test
alignment:       4
tracksRegLiveness: true
body:             |
  bb.1 (%ir-block.0):
    liveins: $x0, $x1

    ; CHECK-LABEL: name: load_store_test
    ; CHECK: liveins: $x0, $x1
    ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
    ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
    ; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load 2 from %ir.ptr, align 4)
    ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
    ; CHECK: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
    ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.ptr + 2, align 4)
    ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
    ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LOAD]], [[C2]](s32)
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[ZEXTLOAD]]
    ; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[OR]](s32)
    ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
    ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY2]], [[C3]](s64)
    ; CHECK: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s64)
    ; CHECK: G_STORE [[COPY2]](s32), [[COPY1]](p0) :: (store 2 into %ir.ptr2, align 4)
    ; CHECK: G_STORE [[LSHR]](s32), [[PTR_ADD1]](p0) :: (store 1 into %ir.ptr2 + 2, align 4)
    ; CHECK: $w0 = COPY [[C]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %0:_(p0) = COPY $x0
    %1:_(p0) = COPY $x1
    %3:_(s32) = G_CONSTANT i32 0
    %2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.ptr, align 4)
    G_STORE %2(s24), %1(p0) :: (store 3 into %ir.ptr2, align 4)
    $w0 = COPY %3(s32)
    RET_ReallyLR implicit $w0

...