)]}'
{
  "commit": "9884fd33dbfe6dc8808a6047f29d8166a6ccb7be",
  "tree": "74eb238e0fe969b80393a7a699a21b6363b55369",
  "parents": [
    "3364284d87035eaac9662d345d4ddee2714f8fd7"
  ],
  "author": {
    "name": "Anton Sidorenko",
    "email": "anton.sidorenko@syntacore.com",
    "time": "Mon Aug 05 17:26:05 2024 +0300"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Aug 05 17:26:05 2024 +0300"
  },
  "message": "[RISCV] Add Syntacore SCR4 RV32/64 processors definition (#101321)\n\nSyntacore SCR4 is a microcontroller-class processor core that has much\r\nin common with SCR3. The most significant difference for compilers is F\r\nand D extensions support. Overview: https://syntacore.com/products/scr4\r\n\r\nTwo CPUs are added:\r\n  * \u0027syntacore-scr4-rv32\u0027 -- rv32imfdc\r\n  * \u0027syntacore-scr4-rv64\u0027 -- rv64imafdc\r\n\r\nScheduling model will be added in a separate PR.\r\n\r\nCo-authored-by: Dmitrii Petrov \u003cdmitrii.petrov@syntacore.com\u003e\r\nCo-authored-by: Anton Afanasyev \u003canton.afanasyev@syntacore.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "26bcda6468dd2b0252a8c50d7d9307299ab6a69f",
      "old_mode": 33188,
      "old_path": "clang/test/Driver/riscv-cpus.c",
      "new_id": "7a885cde76d6ae67d18767a2a7cfd7b83fb177c6",
      "new_mode": 33188,
      "new_path": "clang/test/Driver/riscv-cpus.c"
    },
    {
      "type": "modify",
      "old_id": "e0757b69242a8dc424dbe6a4e400ad0ecfc2b24e",
      "old_mode": 33188,
      "old_path": "clang/test/Misc/target-invalid-cpu-note.c",
      "new_id": "b87bced18cb2b4461873f7cc667ee74c5c7e448e",
      "new_mode": 33188,
      "new_path": "clang/test/Misc/target-invalid-cpu-note.c"
    },
    {
      "type": "modify",
      "old_id": "2486663956c3ff681f1cf735d748f1993b22ff6c",
      "old_mode": 33188,
      "old_path": "llvm/docs/ReleaseNotes.rst",
      "new_id": "a95cb53694e2bb8b28777ebcf49f7b383a78ae05",
      "new_mode": 33188,
      "new_path": "llvm/docs/ReleaseNotes.rst"
    },
    {
      "type": "modify",
      "old_id": "25b24980e0bf65e766ba477ba474e112d6b1d8fb",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVProcessors.td",
      "new_id": "83d27b35cf0da265970f22b469409544028b24b6",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVProcessors.td"
    }
  ]
}