[CodeGen] Fold load into LZCNT/TZCNT/POPCNT after compare elimination in peephole optimizer (#194662)

When a loaded value feeds both a bit-count instruction
(LZCNT/TZCNT/POPCNT) and an `icmp eq zero` / `select` sequence, ISel
emits the register form (`rr`) because the loaded value has two uses at
that point. The peephole optimizer later eliminates the redundant
compare (recognizing that LZCNT/TZCNT/POPCNT already set the necessary
EFLAGS), but failed to retry folding the load into the now single-use
bit-count instruction — because that instruction had already been
scanned.

The fix pre-saves the compared register before `optimizeCmpInstr` erases
the compare. After successful elimination, if the EFLAGS producer and
its defining load are both already-scanned and now have a single use,
fold immediately via `TII->optimizeLoadInstr`.

Before:
```
movq  (%rdi), %rax
lzcntq %rax, %rax
cmovbq %rsi, %rax
```

After:
```
lzcntq (%rdi), %rax
cmovbq %rsi, %rax
```

Fixes #164782