| commit | df96b56b9fad29ff0a8654730952d02e7ef6cc50 | [log] [tgz] |
|---|---|---|
| author | Luke Lau <luke@igalia.com> | Thu Feb 20 12:41:05 2025 +0800 |
| committer | GitHub <noreply@github.com> | Thu Feb 20 12:41:05 2025 +0800 |
| tree | f610f41e71c22cd5942ab0c9f948dfedcdecc283 | |
| parent | 58279d1ee1b567e8ca793d6d1eb6e0f1d5e7279e [diff] |
[RISCV] Move VMV0 elimination past machine SSA opts (#126850) This is the follow up to #125026 that keeps mask operands in virtual register form for as long as possible throughout the backend. The diffs in this patch are from MachineCSE/MachineSink/RISCVVLOptimizer kicking in. The invariant that the mask COPY never has a subreg no longer holds after MachineCSE (it coalesces some copies), so it needed to be relaxed.
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