[mlir][DataLayout] Keep consistent input/output order (#135185)
- Use 'MapVector' instead of 'DenseMap' to keep a consistent order when
importing/printing entries to prevent run-by-run differences.
diff --git a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h
index 50d85a8..ff40bfc 100644
--- a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h
+++ b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.h
@@ -19,6 +19,7 @@
#include "mlir/IR/DialectInterface.h"
#include "mlir/IR/OpDefinition.h"
#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/MapVector.h"
#include "llvm/Support/TypeSize.h"
namespace mlir {
@@ -35,7 +36,7 @@
using TargetDeviceSpecListRef = llvm::ArrayRef<TargetDeviceSpecInterface>;
using TargetDeviceSpecEntry = std::pair<StringAttr, TargetDeviceSpecInterface>;
using DataLayoutIdentifiedEntryMap =
- ::llvm::DenseMap<::mlir::StringAttr, ::mlir::DataLayoutEntryInterface>;
+ ::llvm::MapVector<::mlir::StringAttr, ::mlir::DataLayoutEntryInterface>;
class DataLayoutOpInterface;
class DataLayoutSpecInterface;
class ModuleOp;
diff --git a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td
index fc701b2..c5973d4 100644
--- a/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td
+++ b/mlir/include/mlir/Interfaces/DataLayoutInterfaces.td
@@ -232,9 +232,9 @@
/// identifier they are associated with. Users are not expected to call this
/// method directly.
void bucketEntriesByType(
- ::llvm::DenseMap<::mlir::TypeID, ::mlir::DataLayoutEntryList> &types,
- ::llvm::DenseMap<::mlir::StringAttr,
- ::mlir::DataLayoutEntryInterface> &ids);
+ ::llvm::MapVector<::mlir::TypeID, ::mlir::DataLayoutEntryList> &types,
+ ::llvm::MapVector<::mlir::StringAttr,
+ ::mlir::DataLayoutEntryInterface> &ids);
}];
}
diff --git a/mlir/lib/Dialect/DLTI/DLTI.cpp b/mlir/lib/Dialect/DLTI/DLTI.cpp
index 206d9f4..5d7dd2f 100644
--- a/mlir/lib/Dialect/DLTI/DLTI.cpp
+++ b/mlir/lib/Dialect/DLTI/DLTI.cpp
@@ -14,8 +14,8 @@
#include "mlir/IR/BuiltinTypes.h"
#include "mlir/IR/Dialect.h"
#include "mlir/IR/DialectImplementation.h"
-#include "llvm/ADT/TypeSwitch.h"
+#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
@@ -293,16 +293,16 @@
/// Combines a data layout spec into the given lists of entries organized by
/// type class and identifier, overwriting them if necessary. Fails to combine
/// if the two entries with identical keys are not compatible.
-static LogicalResult
-combineOneSpec(DataLayoutSpecInterface spec,
- DenseMap<TypeID, DataLayoutEntryList> &entriesForType,
- DenseMap<StringAttr, DataLayoutEntryInterface> &entriesForID) {
+static LogicalResult combineOneSpec(
+ DataLayoutSpecInterface spec,
+ llvm::MapVector<TypeID, DataLayoutEntryList> &entriesForType,
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> &entriesForID) {
// A missing spec should be fine.
if (!spec)
return success();
- DenseMap<TypeID, DataLayoutEntryList> newEntriesForType;
- DenseMap<StringAttr, DataLayoutEntryInterface> newEntriesForID;
+ llvm::MapVector<TypeID, DataLayoutEntryList> newEntriesForType;
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> newEntriesForID;
spec.bucketEntriesByType(newEntriesForType, newEntriesForID);
// Combine non-Type DL entries first so they are visible to the
@@ -362,8 +362,8 @@
return {};
// Combine all specs in order, with `this` being the last one.
- DenseMap<TypeID, DataLayoutEntryList> entriesForType;
- DenseMap<StringAttr, DataLayoutEntryInterface> entriesForID;
+ llvm::MapVector<TypeID, DataLayoutEntryList> entriesForType;
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> entriesForID;
for (DataLayoutSpecInterface spec : specs)
if (failed(combineOneSpec(spec, entriesForType, entriesForID)))
return nullptr;
@@ -374,7 +374,7 @@
SmallVector<DataLayoutEntryInterface> entries;
llvm::append_range(entries, llvm::make_second_range(entriesForID));
for (const auto &kvp : entriesForType)
- llvm::append_range(entries, kvp.getSecond());
+ llvm::append_range(entries, kvp.second);
return DataLayoutSpecAttr::get(getContext(), entries);
}
diff --git a/mlir/lib/Interfaces/DataLayoutInterfaces.cpp b/mlir/lib/Interfaces/DataLayoutInterfaces.cpp
index 7afa6ac..9b9bb0c 100644
--- a/mlir/lib/Interfaces/DataLayoutInterfaces.cpp
+++ b/mlir/lib/Interfaces/DataLayoutInterfaces.cpp
@@ -736,8 +736,8 @@
//===----------------------------------------------------------------------===//
void DataLayoutSpecInterface::bucketEntriesByType(
- DenseMap<TypeID, DataLayoutEntryList> &types,
- DenseMap<StringAttr, DataLayoutEntryInterface> &ids) {
+ llvm::MapVector<TypeID, DataLayoutEntryList> &types,
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> &ids) {
for (DataLayoutEntryInterface entry : getEntries()) {
if (auto type = llvm::dyn_cast_if_present<Type>(entry.getKey()))
types[type.getTypeID()].push_back(entry);
@@ -755,8 +755,8 @@
// Second, dispatch verifications of entry groups to types or dialects they
// are associated with.
- DenseMap<TypeID, DataLayoutEntryList> types;
- DenseMap<StringAttr, DataLayoutEntryInterface> ids;
+ llvm::MapVector<TypeID, DataLayoutEntryList> types;
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> ids;
spec.bucketEntriesByType(types, ids);
for (const auto &kvp : types) {
diff --git a/mlir/lib/Target/LLVMIR/DataLayoutImporter.h b/mlir/lib/Target/LLVMIR/DataLayoutImporter.h
index 206c8dd..491ff65 100644
--- a/mlir/lib/Target/LLVMIR/DataLayoutImporter.h
+++ b/mlir/lib/Target/LLVMIR/DataLayoutImporter.h
@@ -17,6 +17,7 @@
#include "mlir/Dialect/LLVMIR/LLVMTypes.h"
#include "mlir/IR/BuiltinAttributes.h"
#include "mlir/Interfaces/DataLayoutInterfaces.h"
+#include "llvm/ADT/MapVector.h"
namespace llvm {
class StringRef;
@@ -110,8 +111,8 @@
std::string layoutStr = {};
StringRef lastToken = {};
SmallVector<StringRef> unhandledTokens;
- DenseMap<StringAttr, DataLayoutEntryInterface> keyEntries;
- DenseMap<TypeAttr, DataLayoutEntryInterface> typeEntries;
+ llvm::MapVector<StringAttr, DataLayoutEntryInterface> keyEntries;
+ llvm::MapVector<TypeAttr, DataLayoutEntryInterface> typeEntries;
MLIRContext *context;
DataLayoutSpecInterface dataLayout;
};
diff --git a/mlir/test/Target/LLVMIR/Import/data-layout.ll b/mlir/test/Target/LLVMIR/Import/data-layout.ll
index d698cae..d6f7719 100644
--- a/mlir/test/Target/LLVMIR/Import/data-layout.ll
+++ b/mlir/test/Target/LLVMIR/Import/data-layout.ll
@@ -4,16 +4,16 @@
; CHECK: dlti.dl_spec =
; CHECK: #dlti.dl_spec<
-; CHECK-DAG: "dlti.endianness" = "little"
-; CHECK-DAG: i1 = dense<8> : vector<2xi64>
-; CHECK-DAG: i8 = dense<8> : vector<2xi64>
-; CHECK-DAG: i16 = dense<16> : vector<2xi64>
-; CHECK-DAG: i32 = dense<32> : vector<2xi64>
-; CHECK-DAG: i64 = dense<[32, 64]> : vector<2xi64>
-; CHECK-DAG: !llvm.ptr = dense<64> : vector<4xi64>
-; CHECK-DAG: f16 = dense<16> : vector<2xi64>
-; CHECK-DAG: f64 = dense<64> : vector<2xi64>
-; CHECK-DAG: f128 = dense<128> : vector<2xi64>
+; CHECK-SAME: !llvm.ptr = dense<64> : vector<4xi64>
+; CHECK-SAME: i1 = dense<8> : vector<2xi64>
+; CHECK-SAME: i8 = dense<8> : vector<2xi64>
+; CHECK-SAME: i16 = dense<16> : vector<2xi64>
+; CHECK-SAME: i32 = dense<32> : vector<2xi64>
+; CHECK-SAME: i64 = dense<[32, 64]> : vector<2xi64>
+; CHECK-SAME: f16 = dense<16> : vector<2xi64>
+; CHECK-SAME: f64 = dense<64> : vector<2xi64>
+; CHECK-SAME: f128 = dense<128> : vector<2xi64>
+; CHECK-SAME: "dlti.endianness" = "little"
; CHECK: >
target datalayout = ""
@@ -21,26 +21,26 @@
; CHECK: dlti.dl_spec =
; CHECK: #dlti.dl_spec<
-; CHECK-DAG: "dlti.endianness" = "little"
-; CHECK-DAG: i64 = dense<64> : vector<2xi64>
-; CHECK-DAG: f80 = dense<128> : vector<2xi64>
-; CHECK-DAG: i8 = dense<8> : vector<2xi64>
-; CHECK-DAG: !llvm.ptr<270> = dense<[32, 64, 64, 32]> : vector<4xi64>
-; CHECK-DAG: !llvm.ptr<271> = dense<32> : vector<4xi64>
-; CHECK-DAG: !llvm.ptr<272> = dense<64> : vector<4xi64>
-; CHECK-DAG: "dlti.stack_alignment" = 128 : i64
-; CHECK-DAG: "dlti.mangling_mode" = "e"
+; CHECK-SAME: !llvm.ptr<270> = dense<[32, 64, 64, 32]> : vector<4xi64>
+; CHECK-SAME: !llvm.ptr<271> = dense<32> : vector<4xi64>
+; CHECK-SAME: !llvm.ptr<272> = dense<64> : vector<4xi64>
+; CHECK-SAME: i64 = dense<64> : vector<2xi64>
+; CHECK-SAME: f80 = dense<128> : vector<2xi64>
+; CHECK-SAME: i8 = dense<8> : vector<2xi64>
+; CHECK-SAME: "dlti.endianness" = "little"
+; CHECK-SAME: "dlti.mangling_mode" = "e"
+; CHECK-SAME: "dlti.stack_alignment" = 128 : i64
target datalayout = "e-m:e-p270:32:64-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
; // -----
; CHECK: dlti.dl_spec =
; CHECK: #dlti.dl_spec<
-; CHECK-DAG: "dlti.endianness" = "big"
-; CHECK-DAG: !llvm.ptr<270> = dense<[16, 32, 64, 8]> : vector<4xi64>
-; CHECK-DAG: !llvm.ptr<271> = dense<[16, 32, 64, 16]> : vector<4xi64>
-; CHECK-DAG: "dlti.alloca_memory_space" = 1 : ui64
-; CHECK-DAG: i64 = dense<[64, 128]> : vector<2xi64>
+; CHECK-SAME: !llvm.ptr<270> = dense<[16, 32, 64, 8]> : vector<4xi64>
+; CHECK-SAME: !llvm.ptr<271> = dense<[16, 32, 64, 16]> : vector<4xi64>
+; CHECK-SAME: i64 = dense<[64, 128]> : vector<2xi64>
+; CHECK-SAME: "dlti.alloca_memory_space" = 1 : ui64
+; CHECK-SAME: "dlti.endianness" = "big"
target datalayout = "A1-E-p270:16:32:64:8-p271:16:32:64-i64:64:128"
; // -----
