[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)
This is based on other targets like PPC/AArch64 and some experiments.
This PR will only enable bidirectional scheduling and tracking register
pressure.
Disclaimer: I haven't tested it on many cores, maybe we should make
some options being features. I believe downstreams must have tried
this before, so feedbacks are welcome.
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
index b911722..2173887 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
@@ -113,10 +113,10 @@
; CHECK-LABEL: trunc_v32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
+; CHECK-NEXT: lui a1, %hi(.LCPI5_0)
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
-; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a0)
+; CHECK-NEXT: flh fa5, %lo(.LCPI5_0)(a1)
; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
@@ -136,10 +136,10 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -157,10 +157,10 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -178,10 +178,10 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v0, v9, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v8, v0.t
@@ -199,10 +199,10 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v0, v10, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t
@@ -220,10 +220,10 @@
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vmfne.vv v0, v8, v8
-; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
-; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: lui a0, 307200
+; CHECK-NEXT: vfadd.vv v8, v8, v8, v0.t
; CHECK-NEXT: fmv.w.x fa5, a0
+; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v0, v12, fa5
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t
