llvm/test/CodeGen/RISCV/pr153598.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=riscv32 -mattr=+zcmp -run-pass=riscv-move-merge -verify-machineinstrs %s -o - | FileCheck %s
---
name: mov-merge
tracksRegLiveness: true
body:             |
  bb.0.entry:
    liveins: $x8, $x9
    ; CHECK-LABEL: name: mov-merge
    ; CHECK: liveins: $x8, $x9
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $x12 = ADDI $x0, -3
    ; CHECK-NEXT: SW renamable $x9, $x2, 56
    ; CHECK-NEXT: CM_MVA01S killed renamable $x9, renamable $x8, implicit-def $x10, implicit-def $x11
    ; CHECK-NEXT: SW renamable $x8, $x2, 60
    ; CHECK-NEXT: PseudoRET
    $x12 = ADDI $x0, -3
    SW renamable $x9, $x2, 56
    $x10 = ADDI killed renamable $x9, 0
    SW renamable $x8, $x2, 60
    $x11 = ADDI killed renamable $x8, 0
    PseudoRET
...