; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=RV64I %s

define <1 x i8> @constraint_vr_fixed(<1 x i8> %0, <1 x i8> %1) nounwind {
; RV32I-LABEL: constraint_vr_fixed:
; RV32I:       # %bb.0:
; RV32I-NEXT:    #APP
; RV32I-NEXT:    vadd.vv v8, v8, v9
; RV32I-NEXT:    #NO_APP
; RV32I-NEXT:    ret
;
; RV64I-LABEL: constraint_vr_fixed:
; RV64I:       # %bb.0:
; RV64I-NEXT:    #APP
; RV64I-NEXT:    vadd.vv v8, v8, v9
; RV64I-NEXT:    #NO_APP
; RV64I-NEXT:    ret
  %a = tail call <1 x i8> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vr"(
    <1 x i8> %0, <1 x i8> %1)
  ret <1 x i8> %a
}

define <4 x i32> @constraint_vd_fixed(<4 x i32> %0, <4 x i32> %1) nounwind {
; RV32I-LABEL: constraint_vd_fixed:
; RV32I:       # %bb.0:
; RV32I-NEXT:    #APP
; RV32I-NEXT:    vadd.vv v8, v8, v9
; RV32I-NEXT:    #NO_APP
; RV32I-NEXT:    ret
;
; RV64I-LABEL: constraint_vd_fixed:
; RV64I:       # %bb.0:
; RV64I-NEXT:    #APP
; RV64I-NEXT:    vadd.vv v8, v8, v9
; RV64I-NEXT:    #NO_APP
; RV64I-NEXT:    ret
  %a = tail call <4 x i32> asm "vadd.vv $0, $1, $2", "=^vd,^vr,^vr"(
    <4 x i32> %0, <4 x i32> %1)
  ret <4 x i32> %a
}

define <16 x i1> @constraint_vm_fixed(<16 x i1> %0, <16 x i1> %1) nounwind {
; RV32I-LABEL: constraint_vm_fixed:
; RV32I:       # %bb.0:
; RV32I-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; RV32I-NEXT:    vmv1r.v v9, v0
; RV32I-NEXT:    vmv1r.v v0, v8
; RV32I-NEXT:    #APP
; RV32I-NEXT:    vadd.vv v0, v9, v0
; RV32I-NEXT:    #NO_APP
; RV32I-NEXT:    ret
;
; RV64I-LABEL: constraint_vm_fixed:
; RV64I:       # %bb.0:
; RV64I-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; RV64I-NEXT:    vmv1r.v v9, v0
; RV64I-NEXT:    vmv1r.v v0, v8
; RV64I-NEXT:    #APP
; RV64I-NEXT:    vadd.vv v0, v9, v0
; RV64I-NEXT:    #NO_APP
; RV64I-NEXT:    ret
  %a = tail call <16 x i1> asm "vadd.vv $0, $1, $2", "=^vr,^vr,^vm"(
    <16 x i1> %0, <16 x i1> %1)
  ret <16 x i1> %a
}