TargetLowering: convert Optional to std::optional
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 83a7c20..a5071ab 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -16,7 +16,6 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/None.h"
-#include "llvm/ADT/Optional.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
@@ -150,18 +149,18 @@
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
const SDValue *Parts, unsigned NumParts,
MVT PartVT, EVT ValueVT, const Value *V,
- Optional<CallingConv::ID> CC);
+ std::optional<CallingConv::ID> CC);
/// getCopyFromParts - Create a value that contains the specified legal parts
/// combined into the value they represent. If the parts combine to a type
/// larger than ValueVT then AssertOp can be used to specify whether the extra
/// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT
/// (ISD::AssertSext).
-static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT, const Value *V,
- Optional<CallingConv::ID> CC = None,
- Optional<ISD::NodeType> AssertOp = None) {
+static SDValue
+getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V,
+ std::optional<CallingConv::ID> CC = std::nullopt,
+ std::optional<ISD::NodeType> AssertOp = std::nullopt) {
// Let the target assemble the parts if it wants to
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts,
@@ -322,7 +321,7 @@
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
const SDValue *Parts, unsigned NumParts,
MVT PartVT, EVT ValueVT, const Value *V,
- Optional<CallingConv::ID> CallConv) {
+ std::optional<CallingConv::ID> CallConv) {
assert(ValueVT.isVector() && "Not a vector value");
assert(NumParts > 0 && "No parts to assemble!");
const bool IsABIRegCopy = CallConv.has_value();
@@ -474,16 +473,16 @@
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
SDValue Val, SDValue *Parts, unsigned NumParts,
MVT PartVT, const Value *V,
- Optional<CallingConv::ID> CallConv);
+ std::optional<CallingConv::ID> CallConv);
/// getCopyToParts - Create a series of nodes that contain the specified value
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
-static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
- const Value *V,
- Optional<CallingConv::ID> CallConv = None,
- ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
+static void
+getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, const Value *V,
+ std::optional<CallingConv::ID> CallConv = std::nullopt,
+ ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
// Let the target split the parts if it wants to
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLI.splitValueIntoRegisterParts(DAG, DL, Val, Parts, NumParts, PartVT,
@@ -656,7 +655,7 @@
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL,
SDValue Val, SDValue *Parts, unsigned NumParts,
MVT PartVT, const Value *V,
- Optional<CallingConv::ID> CallConv) {
+ std::optional<CallingConv::ID> CallConv) {
EVT ValueVT = Val.getValueType();
assert(ValueVT.isVector() && "Not a vector");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -803,13 +802,13 @@
}
RegsForValue::RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt,
- EVT valuevt, Optional<CallingConv::ID> CC)
+ EVT valuevt, std::optional<CallingConv::ID> CC)
: ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
RegCount(1, regs.size()), CallConv(CC) {}
RegsForValue::RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
const DataLayout &DL, unsigned Reg, Type *Ty,
- Optional<CallingConv::ID> CC) {
+ std::optional<CallingConv::ID> CC) {
ComputeValueVTs(TLI, DL, Ty, ValueVTs);
CallConv = CC;
@@ -1443,7 +1442,7 @@
// If this is a PHI node, it may be split up into several MI PHI nodes
// (in FunctionLoweringInfo::set).
RegsForValue RFV(V->getContext(), TLI, DAG.getDataLayout(), Reg,
- V->getType(), None);
+ V->getType(), std::nullopt);
if (RFV.occupiesMultipleRegs()) {
// FIXME: We could potentially support variadic dbg_values here.
if (IsVariadic)
@@ -1511,7 +1510,7 @@
RegsForValue RFV(*DAG.getContext(), DAG.getTargetLoweringInfo(),
DAG.getDataLayout(), InReg, Ty,
- None); // This is not an ABI copy.
+ std::nullopt); // This is not an ABI copy.
SDValue Chain = DAG.getEntryNode();
Result = RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr,
V);
@@ -1707,7 +1706,7 @@
unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
- Inst->getType(), None);
+ Inst->getType(), std::nullopt);
SDValue Chain = DAG.getEntryNode();
return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
}
@@ -10172,7 +10171,7 @@
} else {
// Collect the legal value parts into potentially illegal values
// that correspond to the original function's return values.
- Optional<ISD::NodeType> AssertOp;
+ std::optional<ISD::NodeType> AssertOp;
if (CLI.RetSExt)
AssertOp = ISD::AssertSext;
else if (CLI.RetZExt)
@@ -10663,7 +10662,7 @@
ValueVTs);
MVT VT = ValueVTs[0].getSimpleVT();
MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
- Optional<ISD::NodeType> AssertOp;
+ std::optional<ISD::NodeType> AssertOp;
SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, RegVT, VT,
nullptr, F.getCallingConv(), AssertOp);
@@ -10725,7 +10724,7 @@
// we do generate a copy for it that can be used on return from the
// function.
if (ArgHasUses || isSwiftErrorArg) {
- Optional<ISD::NodeType> AssertOp;
+ std::optional<ISD::NodeType> AssertOp;
if (Arg.hasAttribute(Attribute::SExt))
AssertOp = ISD::AssertSext;
else if (Arg.hasAttribute(Attribute::ZExt))
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
index 4a9521d..4dcf14a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
@@ -33,6 +33,7 @@
#include <algorithm>
#include <cassert>
#include <cstdint>
+#include <optional>
#include <utility>
#include <vector>
@@ -702,14 +703,14 @@
/// Records if this value needs to be treated in an ABI dependant manner,
/// different to normal type legalization.
- Optional<CallingConv::ID> CallConv;
+ std::optional<CallingConv::ID> CallConv;
RegsForValue() = default;
RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt,
- Optional<CallingConv::ID> CC = None);
+ std::optional<CallingConv::ID> CC = std::nullopt);
RegsForValue(LLVMContext &Context, const TargetLowering &TLI,
const DataLayout &DL, unsigned Reg, Type *Ty,
- Optional<CallingConv::ID> CC);
+ std::optional<CallingConv::ID> CC);
bool isABIMangled() const { return CallConv.has_value(); }
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 9cf258d..c76b2ba 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -110,6 +110,7 @@
#include <cstdlib>
#include <iterator>
#include <limits>
+#include <optional>
#include <string>
#include <tuple>
#include <utility>
@@ -4420,7 +4421,7 @@
bool ARMTargetLowering::splitValueIntoRegisterParts(
SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
@@ -4438,7 +4439,7 @@
SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
+ MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
PartVT == MVT::f32) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 7baf55b..18ad564 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -30,6 +30,7 @@
#include "llvm/IR/InlineAsm.h"
#include "llvm/Support/CodeGen.h"
#include "llvm/Support/MachineValueType.h"
+#include <optional>
#include <utility>
namespace llvm {
@@ -888,16 +889,15 @@
MachineBasicBlock *Entry,
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
- bool
- splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
- Optional<CallingConv::ID> CC) const override;
+ bool splitValueIntoRegisterParts(
+ SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
+ const override;
- SDValue
- joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT,
- Optional<CallingConv::ID> CC) const override;
+ SDValue joinRegisterPartsIntoValue(
+ SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, EVT ValueVT,
+ std::optional<CallingConv::ID> CC) const override;
SDValue
LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 5f51bdd..9d5dbffc 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -96,6 +96,7 @@
#include <cstdint>
#include <iterator>
#include <list>
+#include <optional>
#include <utility>
#include <vector>
@@ -18024,7 +18025,7 @@
bool PPCTargetLowering::splitValueIntoRegisterParts(
SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
EVT ValVT = Val.getValueType();
// If we are splitting a scalar integer into f64 parts (i.e. so they
// can be placed into VFRC registers), we need to zero extend and
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index 4113508..0c5d694 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -29,6 +29,7 @@
#include "llvm/IR/Metadata.h"
#include "llvm/IR/Type.h"
#include "llvm/Support/MachineValueType.h"
+#include <optional>
#include <utility>
namespace llvm {
@@ -1162,10 +1163,10 @@
PPC::AddrMode SelectForceXFormMode(SDValue N, SDValue &Disp, SDValue &Base,
SelectionDAG &DAG) const;
- bool
- splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
- Optional<CallingConv::ID> CC) const override;
+ bool splitValueIntoRegisterParts(
+ SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
+ const override;
/// Structure that collects some common arguments that get passed around
/// between the functions for call lowering.
struct CallFlags {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 34b0ec4..44d3b05 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13351,7 +13351,7 @@
bool RISCVTargetLowering::splitValueIntoRegisterParts(
SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) {
@@ -13405,7 +13405,7 @@
SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
+ MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) {
SDValue Val = Parts[0];
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 807f3ea..35c18b9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/TargetParser.h"
+#include <optional>
namespace llvm {
class RISCVSubtarget;
@@ -551,16 +552,15 @@
MachineMemOperand::Flags Flags = MachineMemOperand::MONone,
unsigned *Fast = nullptr) const override;
- bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL,
- SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT,
- Optional<CallingConv::ID> CC) const override;
+ bool splitValueIntoRegisterParts(
+ SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
+ const override;
- SDValue
- joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT,
- Optional<CallingConv::ID> CC) const override;
+ SDValue joinRegisterPartsIntoValue(
+ SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, EVT ValueVT,
+ std::optional<CallingConv::ID> CC) const override;
static RISCVII::VLMUL getLMUL(MVT VT);
inline static unsigned computeVLMAX(unsigned VectorBits, unsigned EltSize,
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 01f47e6..6a79af6 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -25,6 +25,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include <cctype>
+#include <optional>
using namespace llvm;
@@ -1450,7 +1451,7 @@
bool SystemZTargetLowering::splitValueIntoRegisterParts(
SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
EVT ValueVT = Val.getValueType();
assert((ValueVT != MVT::i128 ||
((NumParts == 1 && PartVT == MVT::Untyped) ||
@@ -1466,7 +1467,7 @@
SDValue SystemZTargetLowering::joinRegisterPartsIntoValue(
SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
+ MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
assert((ValueVT != MVT::i128 ||
((NumParts == 1 && PartVT == MVT::Untyped) ||
(NumParts == 2 && PartVT == MVT::i64))) &&
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index ed8e450..2ab9cb7 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -19,6 +19,7 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h"
+#include <optional>
namespace llvm {
namespace SystemZISD {
@@ -417,7 +418,7 @@
}
unsigned
getNumRegisters(LLVMContext &Context, EVT VT,
- Optional<MVT> RegisterVT) const override {
+ std::optional<MVT> RegisterVT) const override {
// i128 inline assembly operand.
if (VT == MVT::i128 && RegisterVT && *RegisterVT == MVT::Untyped)
return 1;
@@ -556,15 +557,14 @@
const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
bool allowTruncateForTailCall(Type *, Type *) const override;
bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
- bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL,
- SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT,
- Optional<CallingConv::ID> CC) const override;
- SDValue
- joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT,
- Optional<CallingConv::ID> CC) const override;
+ bool splitValueIntoRegisterParts(
+ SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
+ const override;
+ SDValue joinRegisterPartsIntoValue(
+ SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, EVT ValueVT,
+ std::optional<CallingConv::ID> CC) const override;
SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins,
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 3acbe7d..f445550 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2777,7 +2777,7 @@
bool X86TargetLowering::splitValueIntoRegisterParts(
SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
- unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
EVT ValueVT = Val.getValueType();
if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
@@ -2794,7 +2794,7 @@
SDValue X86TargetLowering::joinRegisterPartsIntoValue(
SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
+ MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
bool IsABIRegCopy = CC.has_value();
if (IsABIRegCopy && ValueVT == MVT::bf16 && PartVT == MVT::f32) {
unsigned ValueBits = ValueVT.getSizeInBits();
diff --git a/llvm/lib/Target/X86/X86ISelLowering.h b/llvm/lib/Target/X86/X86ISelLowering.h
index 2776fa0..d1c0ee4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.h
+++ b/llvm/lib/Target/X86/X86ISelLowering.h
@@ -1654,16 +1654,15 @@
MachineBasicBlock *Entry,
const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
- bool
- splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
- Optional<CallingConv::ID> CC) const override;
+ bool splitValueIntoRegisterParts(
+ SelectionDAG & DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
+ unsigned NumParts, MVT PartVT, std::optional<CallingConv::ID> CC)
+ const override;
- SDValue
- joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL,
- const SDValue *Parts, unsigned NumParts,
- MVT PartVT, EVT ValueVT,
- Optional<CallingConv::ID> CC) const override;
+ SDValue joinRegisterPartsIntoValue(
+ SelectionDAG & DAG, const SDLoc &DL, const SDValue *Parts,
+ unsigned NumParts, MVT PartVT, EVT ValueVT,
+ std::optional<CallingConv::ID> CC) const override;
bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
