)]}'
{
  "commit": "82049310385d5222527cf7d12984bd8d4f955dd1",
  "tree": "c15924a4ff44a84a3f8ed3c6566b4a0bea50646b",
  "parents": [
    "dfc60b2ceb50e75dc07bdda18ae74695f18b370c"
  ],
  "author": {
    "name": "Luke Lau",
    "email": "luke@igalia.com",
    "time": "Wed Apr 23 15:17:04 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Apr 23 15:17:04 2025 +0800"
  },
  "message": "[RISCV] Add disjoint or patterns for vwadd[u].v{v,x} (#136716)\n\nDAGCombiner::hoistLogicOpWithSameOpcodeHands will hoist\n\n(or disjoint (ext a), (ext b)) -\u003e (ext (or disjoint a, b))\n\nSo this adds patterns to match vwadd[u].v{v,x} in this case.\n\nWe have to teach the combine to preserve the disjoint flag.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b571f635c744fafd77bdb42cadf0a66fbc20460b",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp",
      "new_id": "62559229793997ac12d4ceffbc2907dc44511479",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp"
    },
    {
      "type": "modify",
      "old_id": "b2c5261ae6c2de22e81a1849bda5b2c798250e37",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td",
      "new_id": "aea125c5348dd0ff32b22cea0a7d15fb8bbac5f9",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td"
    },
    {
      "type": "modify",
      "old_id": "3f5d42f89337bb37566d4d8fd33824b0d23fe3d6",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll",
      "new_id": "f94e46771f49ceb4aa2c8dbff22bdc136f704006",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll"
    }
  ]
}