)]}'
{
  "commit": "7f3d91d14ae33a8206b536ac1ffe69565423ced3",
  "tree": "4646a085ea5564aa914ce6f01eeabb8f2e8c5ec5",
  "parents": [
    "34b0a6e6d863a6f91698b435c72e69fcfebf13f2"
  ],
  "author": {
    "name": "Zeyi Xu",
    "email": "mitchell.xu2@gmail.com",
    "time": "Thu Jul 09 11:29:43 2026 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jul 09 11:29:43 2026 +0800"
  },
  "message": "[RISCV][MCA] Avoid deriving EMUL without SEW (#207986)\n\nWhen only an LMUL instrument is active, SEW is unavailable. Avoid\nderiving EMUL for vector memory instructions in that case and fall back\nto the base scheduling class.\n\nCloses #170118.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1270cdd8189d9bb00638e8f7e8510154e6c60df2",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp",
      "new_id": "8f8af225ce686970c2e416c34cc354ec8f8e4a7b",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp"
    },
    {
      "type": "modify",
      "old_id": "747cfca51e4dc3253affe4400ea76214a9e84f6f",
      "old_mode": 33188,
      "old_path": "llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s",
      "new_id": "a48a65a7528f347b31b8a2bdedb905aaadc46e7c",
      "new_mode": 33188,
      "new_path": "llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s"
    }
  ]
}