llvm/test/Transforms/SCCP/pr52253.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=sccp -S | FileCheck %s

define i1 @foo(i32 %t4, i32 %t10) {
; CHECK-LABEL: @foo(
; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
; CHECK-NEXT:    [[T14:%.*]] = zext i1 [[T12]] to i32
; CHECK-NEXT:    [[T15:%.*]] = shl i32 [[T4]], [[T14]]
; CHECK-NEXT:    [[T17:%.*]] = and i32 [[T15]], 255
; CHECK-NEXT:    ret i1 false
;
  %t09 = shl i32 %t10, 24
  %t010 = ashr exact i32 %t09, 24
  %t011 = add nsw i32 %t010, 979
  %t11 = trunc i32 %t4 to i8
  %t12 = icmp eq i8 %t11, 0
  %t14 = zext i1 %t12 to i32
  %t15 = shl i32 %t4, %t14
  %t17 = and i32 %t15, 255
  %t18 = icmp eq i32 %t011, %t17
  ret i1 %t18
}

define i1 @bar(i32 %t4, i32 %t10) {
; CHECK-LABEL: @bar(
; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
; CHECK-NEXT:    [[T14:%.*]] = zext i1 [[T12]] to i8
; CHECK-NEXT:    [[T15:%.*]] = shl i8 [[T11]], [[T14]]
; CHECK-NEXT:    [[T17:%.*]] = zext i8 [[T15]] to i32
; CHECK-NEXT:    ret i1 false
;
  %t09 = shl i32 %t10, 24
  %t010 = ashr exact i32 %t09, 24
  %t011 = add nsw i32 %t010, 979
  %t11 = trunc i32 %t4 to i8
  %t12 = icmp eq i8 %t11, 0
  %t14 = zext i1 %t12 to i8
  %t15 = shl i8 %t11, %t14
  %t17 = zext i8 %t15 to i32
  %t18 = icmp eq i32 %t011, %t17
  ret i1 %t18
}

define i1 @foobar(i32 %t4, i32 %t10) {
; CHECK-LABEL: @foobar(
; CHECK-NEXT:    [[T09:%.*]] = shl i32 [[T10:%.*]], 24
; CHECK-NEXT:    [[T010:%.*]] = ashr exact i32 [[T09]], 24
; CHECK-NEXT:    [[T011:%.*]] = add nsw i32 [[T010]], 979
; CHECK-NEXT:    [[T11:%.*]] = trunc i32 [[T4:%.*]] to i8
; CHECK-NEXT:    [[T12:%.*]] = icmp eq i8 [[T11]], 0
; CHECK-NEXT:    [[T13:%.*]] = zext i8 [[T11]] to i32
; CHECK-NEXT:    [[T14:%.*]] = select i1 [[T12]], i32 1, i32 0
; CHECK-NEXT:    [[T15:%.*]] = shl nuw nsw i32 [[T13]], [[T14]]
; CHECK-NEXT:    [[T16:%.*]] = trunc i32 [[T15]] to i8
; CHECK-NEXT:    [[T17:%.*]] = zext i8 [[T16]] to i32
; CHECK-NEXT:    ret i1 false
;
  %t09 = shl i32 %t10, 24
  %t010 = ashr exact i32 %t09, 24
  %t011 = add nsw i32 %t010, 979

  %t11 = trunc i32 %t4 to i8
  %t12 = icmp eq i8 %t11, 0
  %t13 = zext i8 %t11 to i32
  %t14 = select i1 %t12, i32 1, i32 0
  %t15 = shl nuw nsw i32 %t13, %t14
  %t16 = trunc i32 %t15 to i8
  %t17 = zext i8 %t16 to i32

  %t18 = icmp eq i32 %t011, %t17
  ret i1 %t18
}