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====================================================================================
Syntax of Core GFX10 Instructions
====================================================================================

.. contents::
  :local:

Introduction
============

This document describes the syntax of *core* GFX10 instructions.

Notation
========

Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.

Overview
========

An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this document<amdgpu_syn_instructions>`.

Instructions
============


DPP16
-----------------------

.. parsed-literal::

    **INSTRUCTION**              **DST0**       **DST1** **SRC0**       **SRC1**      **SRC2**  **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_add_co_ci_u32_dpp      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_add_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_add_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_add_nc_u32_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_and_b32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ashrrev_i32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_bfrev_b32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ceil_f16_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ceil_f32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cndmask_b32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cos_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cos_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f16_f32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f16_i16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f16_u16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_f16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_i32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_u32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_ubyte0_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_ubyte1_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_ubyte2_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_f32_ubyte3_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_flr_i32_f32_dpp    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_i16_f16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_i32_f32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_norm_i16_f16_dpp   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_norm_u16_f16_dpp   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_off_f32_i4_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_rpi_i32_f32_dpp    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_u16_f16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_cvt_u32_f32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_exp_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_exp_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ffbh_i32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ffbh_u32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ffbl_b32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_floor_f16_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_floor_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_fmac_f16_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_fmac_f32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_fract_f16_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_fract_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_frexp_exp_i16_f16_dpp  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_frexp_exp_i32_f32_dpp  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_frexp_mant_f16_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_frexp_mant_f32_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_ldexp_f16_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_log_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_log_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_lshlrev_b32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_lshrrev_b32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mac_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_max_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_max_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_max_i32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_max_u32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_min_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_min_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_min_i32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_min_u32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mov_b32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_movreld_b32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_movrels_b32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_movrelsd_2_b32_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_movrelsd_b32_dpp       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_hi_i32_i24_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_hi_u32_u24_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_i32_i24_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_legacy_f32_dpp     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_mul_u32_u24_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_not_b32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_or_b32_dpp             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rcp_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rcp_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rcp_iflag_f32_dpp      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rndne_f16_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rndne_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rsq_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_rsq_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sat_pk_u8_i16_dpp      :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                       :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sin_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sin_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sqrt_f16_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sqrt_f32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sub_co_ci_u32_dpp      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sub_f16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sub_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_sub_nc_u32_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_subrev_co_ci_u32_dpp   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_subrev_f16_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_subrev_f32_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,   :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_subrev_nc_u32_dpp      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_trunc_f16_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_trunc_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_xnor_b32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
    v_xor_b32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`           :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`

DPP8
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST0**       **DST1**      **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_add_co_ci_u32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_add_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_add_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_add_nc_u32_dpp               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_and_b32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ashrrev_i32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_bfrev_b32_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ceil_f16_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ceil_f32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cndmask_b32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cos_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cos_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f16_f32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f16_i16_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f16_u16_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_f16_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_i32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_u32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_ubyte0_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_ubyte1_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_ubyte2_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_f32_ubyte3_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_flr_i32_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_i16_f16_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_i32_f32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_norm_i16_f16_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_norm_u16_f16_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_off_f32_i4_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_rpi_i32_f32_dpp          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_u16_f16_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_cvt_u32_f32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_exp_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_exp_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ffbh_i32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ffbh_u32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ffbl_b32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_floor_f16_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_floor_f32_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_fmac_f16_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_fmac_f32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_fract_f16_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_fract_f32_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_frexp_exp_i16_f16_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_frexp_exp_i32_f32_dpp        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_frexp_mant_f16_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_frexp_mant_f32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_ldexp_f16_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_log_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_log_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_lshlrev_b32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_lshrrev_b32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mac_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_max_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_max_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_max_i32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_max_u32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_min_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_min_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_min_i32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_min_u32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mov_b32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_movreld_b32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_movrels_b32_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_movrelsd_2_b32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_movrelsd_b32_dpp             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_hi_i32_i24_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_hi_u32_u24_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_i32_i24_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_legacy_f32_dpp           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_mul_u32_u24_dpp              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_not_b32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_or_b32_dpp                   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rcp_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rcp_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rcp_iflag_f32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rndne_f16_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rndne_f32_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rsq_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_rsq_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sat_pk_u8_i16_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sin_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sin_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sqrt_f16_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sqrt_f32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sub_co_ci_u32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sub_f16_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sub_f32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_sub_nc_u32_dpp               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_subrev_co_ci_u32_dpp         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_subrev_f16_dpp               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_subrev_f32_dpp               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_subrev_nc_u32_dpp            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_trunc_f16_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_trunc_f32_dpp                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_xnor_b32_dpp                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
    v_xor_b32_dpp                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`

DS
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**         **SRC0**      **SRC1**      **SRC2**           **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    ds_add_f32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_rtn_f32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_src2_f32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_add_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_b32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_b64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_rtn_b32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_rtn_b64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_src2_b32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_and_src2_b64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_append                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`                                           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_bpermute_b32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>`
    ds_cmpst_b32                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_b64                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_f32                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_f64                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_rtn_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_rtn_b64               :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_rtn_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_cmpst_rtn_f64               :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_condxchg32_rtn_b64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_consume                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`                                           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_dec_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_barrier                             :ref:`vdata<amdgpu_synid_gfx10_vdata>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_init                                :ref:`vdata<amdgpu_synid_gfx10_vdata>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_sema_br                             :ref:`vdata<amdgpu_synid_gfx10_vdata>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_sema_p                                                                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_sema_release_all                                                       :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_gws_sema_v                                                                 :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_inc_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_f32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_f64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_i32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_i64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_f32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_f64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_i32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_i64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_f32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_f64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_i32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_i64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_max_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_f32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_f64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_i32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_i64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_f32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_f64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_i32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_i64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_f32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_f64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_i32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_i64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_min_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_mskor_b32                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_mskor_b64                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_mskor_rtn_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_mskor_rtn_b64               :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_nop
    ds_or_b32                                  :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_or_b64                                  :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_or_rtn_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_or_rtn_b64                  :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_or_src2_b32                             :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_or_src2_b64                             :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_ordered_count               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_permute_b32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>`
    ds_read2_b32                   :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_read2_b64                   :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_read2st64_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_read2st64_b64               :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_addtid_b32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`                                           :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_b128                   :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_b32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_b64                    :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_b96                    :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_i16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_i8                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_i8_d16                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_i8_d16_hi              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u16_d16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u16_d16_hi             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u8                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u8_d16                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_read_u8_d16_hi              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_rtn_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_rtn_u64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_src2_u32                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_src2_u64                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_u32                                :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_rsub_u64                                :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_rtn_u32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_rtn_u64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_src2_u32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_src2_u64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_u32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_sub_u64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_swizzle_b32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`pattern<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrap_rtn_b32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write2_b32                              :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_write2_b64                              :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_addtid_b32                        :ref:`vdata<amdgpu_synid_gfx10_vdata>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b128                              :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b16                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b16_d16_hi                        :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b32                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b64                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b8                                :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b8_d16_hi                         :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_b96                               :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_src2_b32                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_write_src2_b64                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg2_rtn_b32             :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg2_rtn_b64             :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg2st64_rtn_b32         :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg2st64_rtn_b64         :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata0<amdgpu_synid_gfx10_vdata0_1>`,   :ref:`vdata1<amdgpu_synid_gfx10_vdata1_1>`         :ref:`offset0<amdgpu_synid_ds_offset80>` :ref:`offset1<amdgpu_synid_ds_offset81>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg_rtn_b32              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_wrxchg_rtn_b64              :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_b32                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_b64                                 :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_rtn_b32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_rtn_b64                 :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                    :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_src2_b32                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
    ds_xor_src2_b64                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr>`                              :ref:`offset<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`

EXP
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**      **SRC2**      **SRC3**           **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    exp                            :ref:`tgt<amdgpu_synid_gfx10_tgt>`,      :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_1>`,    :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_1>`,    :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_1>`,    :ref:`vsrc3<amdgpu_synid_gfx10_vsrc_1>`          :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>`

FLAT
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**           **SRC0**      **SRC1**         **SRC2**       **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    flat_atomic_add                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_add_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_and                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_and_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_cmpswap            :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_cmpswap_x2         :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_dec                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_dec_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fcmpswap           :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fcmpswap_x2        :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fmax               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fmax_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fmin               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_fmin_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_inc                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_inc_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_or                 :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_or_x2              :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_smax               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_smax_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_smin               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_smin_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_sub                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_sub_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_swap               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_swap_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_umax               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_umax_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_umin               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_umin_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`               :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_xor                :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_atomic_xor_x2             :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    flat_load_dword                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_dwordx2              :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_dwordx3              :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_dwordx4              :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_sbyte                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_sbyte_d16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_sbyte_d16_hi         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_short_d16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_short_d16_hi         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_sshort               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_ubyte                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_ubyte_d16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_ubyte_d16_hi         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_load_ushort               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`                             :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_byte                              :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_byte_d16_hi                       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_dword                             :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_dwordx2                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_dwordx3                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_short                             :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    flat_store_short_d16_hi                      :ref:`vaddr<amdgpu_synid_gfx10_vaddr_1>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`                   :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_atomic_add              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_add_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_and              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_and_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_cmpswap          :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_cmpswap_x2       :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_dec              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_dec_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_fmax             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_fmax_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_fmin             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_fmin_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_inc              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_inc_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_or               :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_or_x2            :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_smax             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_smax_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_smin             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_smin_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_sub              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_sub_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_swap             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_swap_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_umax             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_umax_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_umin             :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_umin_x2          :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_xor              :ref:`vdst<amdgpu_synid_gfx10_vdst_4>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_atomic_xor_x2           :ref:`vdst<amdgpu_synid_gfx10_vdst_5>`::ref:`opt<amdgpu_synid_gfx10_opt>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    global_load_dword              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_dwordx2            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_dwordx3            :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_dwordx4            :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_sbyte              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_sbyte_d16          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_short_d16          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_short_d16_hi       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_sshort             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_ubyte              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_ubyte_d16          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_load_ushort             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_byte                            :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_byte_d16_hi                     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_dword                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_dwordx2                         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_dwordx3                         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_dwordx4                         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_short                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    global_store_short_d16_hi                    :ref:`vaddr<amdgpu_synid_gfx10_vaddr_2>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_dword             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_dwordx2           :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_dwordx3           :ref:`vdst<amdgpu_synid_gfx10_vdst_3>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_dwordx4           :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_sbyte             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_sbyte_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_sbyte_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_short_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_short_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_sshort            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_ubyte             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_ubyte_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_ubyte_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_load_ushort            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,         :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`                   :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_byte                           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_byte_d16_hi                    :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_dword                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_dwordx2                        :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_dwordx3                        :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_dwordx4                        :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_short                          :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    scratch_store_short_d16_hi                   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_3>`,    :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`saddr<amdgpu_synid_gfx10_saddr_1>`      :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`

MIMG
-----------------------

.. parsed-literal::

    **INSTRUCTION**                 **DST**   **SRC0**       **SRC1**   **SRC2**   **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    image_atomic_add                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_and                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_cmpswap              :ref:`vdata<amdgpu_synid_gfx10_vdata_5>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_dec                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_fcmpswap             :ref:`vdata<amdgpu_synid_gfx10_vdata_5>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_fmax                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_fmin                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_inc                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_or                   :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_smax                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_smin                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_sub                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_swap                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_umax                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_umin                 :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_atomic_xor                  :ref:`vdata<amdgpu_synid_gfx10_vdata_4>`::ref:`dst<amdgpu_synid_gfx10_dst>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_gather4               :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_b             :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_b_cl          :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_b_cl_o        :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_b_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c             :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_b           :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_b_cl        :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_b_cl_o      :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_b_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_cl          :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_cl_o        :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_l           :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_l_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_lz          :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_lz_o        :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_c_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_cl            :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_cl_o          :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_l             :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_l_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_lz            :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_lz_o          :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_gather4_o             :ref:`vdst<amdgpu_synid_gfx10_vdst_6>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_get_lod               :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_get_resinfo           :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_load                  :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_load_mip              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_load_mip_pck          :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_load_mip_pck_sgn      :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_load_pck              :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_load_pck_sgn          :ref:`vdst<amdgpu_synid_gfx10_vdst_7>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`         :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
    image_sample                :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_b              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_b_cl           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_b_cl_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_b_o            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_b            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_b_cl         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_b_cl_o       :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_b_o          :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_cl        :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_cl_g16    :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_cl_o      :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_cl_o_g16  :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_g16       :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cd_o_g16     :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cl           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_cl_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_cl         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_cl_g16     :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_cl_o       :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_cl_o_g16   :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_g16        :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_o          :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_d_o_g16      :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_l            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_l_o          :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_lz           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_lz_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_c_o            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd             :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_cl          :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_cl_g16      :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_cl_o        :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_cl_o_g16    :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_g16         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cd_o_g16       :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cl             :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_cl_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_cl           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_cl_g16       :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_cl_o         :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_cl_o_g16     :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_g16          :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_o            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_d_o_g16        :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_l              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_l_o            :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_lz             :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_lz_o           :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_sample_o              :ref:`vdst<amdgpu_synid_gfx10_vdst_8>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`,     :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`, :ref:`ssamp<amdgpu_synid_gfx10_ssamp>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_store                       :ref:`vdata<amdgpu_synid_gfx10_vdata_6>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_store_mip                   :ref:`vdata<amdgpu_synid_gfx10_vdata_6>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
    image_store_mip_pck               :ref:`vdata<amdgpu_synid_gfx10_vdata_7>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`
    image_store_pck                   :ref:`vdata<amdgpu_synid_gfx10_vdata_7>`,     :ref:`vaddr<amdgpu_synid_gfx10_vaddr_4>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc>`  :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>`

MTBUF
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**   **SRC0**   **SRC1**   **SRC2**    **SRC3**     **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    tbuffer_load_format_d16_x      :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_d16_xy     :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_d16_xyz    :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_d16_xyzw   :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_x          :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_xy         :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_xyz        :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_load_format_xyzw       :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    tbuffer_store_format_d16_x           :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_d16_xy          :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_d16_xyz         :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_d16_xyzw        :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_x               :ref:`vdata<amdgpu_synid_gfx10_vdata>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_xy              :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_xyz             :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    tbuffer_store_format_xyzw            :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`

MUBUF
-----------------------

.. parsed-literal::

    **INSTRUCTION**                   **DST**   **SRC0**             **SRC1**   **SRC2**    **SRC3**     **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    buffer_atomic_add                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_add_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_and                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_and_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_cmpswap               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_cmpswap_x2            :ref:`vdata<amdgpu_synid_gfx10_vdata_10>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_dec                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_dec_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fcmpswap              :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fcmpswap_x2           :ref:`vdata<amdgpu_synid_gfx10_vdata_10>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fmax                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fmax_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fmin                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_fmin_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`f64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_inc                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_inc_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_or                    :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_or_x2                 :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_smax                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_smax_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_smin                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_smin_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_sub                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_sub_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_swap                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_swap_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_umax                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_umax_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_umin                  :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_umin_x2               :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_xor                   :ref:`vdata<amdgpu_synid_gfx10_vdata_8>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_atomic_xor_x2                :ref:`vdata<amdgpu_synid_gfx10_vdata_9>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_gl0_inv
    buffer_gl1_inv
    buffer_load_dword             :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_load_dwordx2           :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_dwordx3           :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_dwordx4           :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_d16_x      :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_d16_xy     :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_d16_xyz    :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_d16_xyzw   :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_x          :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_load_format_xy         :ref:`vdst<amdgpu_synid_gfx10_vdst_10>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_xyz        :ref:`vdst<amdgpu_synid_gfx10_vdst_11>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_format_xyzw       :ref:`vdst<amdgpu_synid_gfx10_vdst_12>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_sbyte             :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_load_sbyte_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_sbyte_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_short_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_short_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_sshort            :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_load_ubyte             :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_load_ubyte_d16         :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_ubyte_d16_hi      :ref:`vdst<amdgpu_synid_gfx10_vdst_9>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
    buffer_load_ushort            :ref:`vdst<amdgpu_synid_gfx10_vdst_13>`, :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`,           :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`, :ref:`soffset<amdgpu_synid_gfx10_soffset>`          :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`lds<amdgpu_synid_lds>`
    buffer_store_byte                   :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_byte_d16_hi            :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_dword                  :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_dwordx2                :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_dwordx3                :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_dwordx4                :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_d16_x           :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_d16_xy          :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_d16_xyz         :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_d16_xyzw        :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_x               :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_xy              :ref:`vdata<amdgpu_synid_gfx10_vdata_1>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_xyz             :ref:`vdata<amdgpu_synid_gfx10_vdata_3>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_format_xyzw            :ref:`vdata<amdgpu_synid_gfx10_vdata_2>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_short                  :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
    buffer_store_short_d16_hi           :ref:`vdata<amdgpu_synid_gfx10_vdata>`,           :ref:`vaddr<amdgpu_synid_gfx10_vaddr_5>`, :ref:`srsrc<amdgpu_synid_gfx10_srsrc_1>`,  :ref:`soffset<amdgpu_synid_gfx10_soffset>`  :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`

SDWA
-----------------------

.. parsed-literal::

    **INSTRUCTION**               **DST0**       **DST1** **SRC0**        **SRC1**       **SRC2**  **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_add_co_ci_u32_sdwa      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_add_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_add_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_add_nc_u32_sdwa         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_and_b32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_ashrrev_i32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_bfrev_b32_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ceil_f16_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ceil_f32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cmp_class_f16_sdwa      :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`       :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_class_f32_sdwa      :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`       :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_eq_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_f_f16_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_f_f32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_f_i32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_f_u32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ge_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_gt_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_le_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lg_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lg_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_f16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_f32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_lt_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ne_i16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ne_i32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ne_u16_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ne_u32_sdwa         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_neq_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_neq_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nge_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nge_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ngt_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_ngt_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nle_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nle_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nlg_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nlg_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nlt_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_nlt_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_o_f16_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_o_f32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_t_i32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_t_u32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_tru_f16_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_tru_f32_sdwa        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_u_f16_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmp_u_f32_sdwa          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_class_f16_sdwa                     :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`       :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_class_f32_sdwa                     :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`       :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_eq_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_f_f16_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_f_f32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_f_i32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_f_u32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ge_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_gt_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_le_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lg_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lg_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_f16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_f32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_lt_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ne_i16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ne_i32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ne_u16_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ne_u32_sdwa                        :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_neq_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_neq_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nge_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nge_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ngt_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_ngt_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nle_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nle_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nlg_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nlg_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nlt_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_nlt_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_o_f16_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_o_f32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_t_i32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_t_u32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_tru_f16_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_tru_f32_sdwa                       :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_u_f16_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cmpx_u_f32_sdwa                         :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cndmask_b32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_cos_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cos_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f16_f32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f16_i16_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f16_u16_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src_1>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_f16_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_i32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_u32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_ubyte0_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_ubyte1_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_ubyte2_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_f32_ubyte3_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_flr_i32_f32_sdwa    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_i16_f16_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_i32_f32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_norm_i16_f16_sdwa   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_norm_u16_f16_sdwa   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_off_f32_i4_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_rpi_i32_f32_sdwa    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_u16_f16_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_cvt_u32_f32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_exp_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_exp_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ffbh_i32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ffbh_u32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ffbl_b32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_floor_f16_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_floor_f32_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_fract_f16_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_fract_f32_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_frexp_exp_i16_f16_sdwa  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_frexp_exp_i32_f32_sdwa  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_frexp_mant_f16_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_frexp_mant_f32_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_ldexp_f16_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_log_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_log_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_lshlrev_b32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_lshrrev_b32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_max_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_max_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_max_i32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_max_u32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_min_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_min_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_min_i32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_min_u32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mov_b32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_movreld_b32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_movrels_b32_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_movrelsd_2_b32_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_movrelsd_b32_sdwa       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m_1>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_mul_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_hi_i32_i24_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_hi_u32_u24_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_i32_i24_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_legacy_f32_sdwa     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_mul_u32_u24_sdwa        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_not_b32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_or_b32_sdwa             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_rcp_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rcp_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rcp_iflag_f32_sdwa      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rndne_f16_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rndne_f32_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rsq_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_rsq_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sat_pk_u8_i16_sdwa      :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,      :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`                        :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sin_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sin_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sqrt_f16_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sqrt_f32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_sub_co_ci_u32_sdwa      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_sub_f16_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_sub_f32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_sub_nc_u32_sdwa         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_subrev_co_ci_u32_sdwa   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_subrev_f16_sdwa         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_subrev_f32_sdwa         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_subrev_nc_u32_sdwa      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_trunc_f16_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_trunc_f32_sdwa          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m>`                        :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
    v_xnor_b32_sdwa           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
    v_xor_b32_sdwa            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,           :ref:`src0<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`,     :ref:`src1<amdgpu_synid_gfx10_src>`::ref:`m<amdgpu_synid_gfx10_m_1>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`

SMEM
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**             **SRC1**      **SRC2**           **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_atc_probe                              :ref:`probe<amdgpu_synid_gfx10_probe>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
    s_atc_probe_buffer                       :ref:`probe<amdgpu_synid_gfx10_probe>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`
    s_atomic_add                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_add_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_and                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_and_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_cmpswap                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_cmpswap_x2                      :ref:`sdata<amdgpu_synid_gfx10_sdata_2>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_dec                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_dec_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_inc                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_inc_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_or                              :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_or_x2                           :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_smax                            :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_smax_x2                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_smin                            :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_smin_x2                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_sub                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_sub_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_swap                            :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_swap_x2                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_umax                            :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_umax_x2                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_umin                            :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_umin_x2                         :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_xor                             :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_atomic_xor_x2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_add                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_add_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_and                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_and_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_cmpswap                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b32x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_cmpswap_x2               :ref:`sdata<amdgpu_synid_gfx10_sdata_2>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`b64x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_dec                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_dec_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_inc                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_inc_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_or                       :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_or_x2                    :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_smax                     :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_smax_x2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_smin                     :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_smin_x2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_sub                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_sub_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_swap                     :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_swap_x2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_umax                     :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_umax_x2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_umin                     :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_umin_x2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`,   :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_xor                      :ref:`sdata<amdgpu_synid_gfx10_sdata>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_atomic_xor_x2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_1>`::ref:`dst<amdgpu_synid_gfx10_dst>`,       :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_load_dword            :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_buffer_load_dwordx16         :ref:`sdst<amdgpu_synid_gfx10_sdst_2>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_buffer_load_dwordx2          :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_buffer_load_dwordx4          :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_buffer_load_dwordx8          :ref:`sdst<amdgpu_synid_gfx10_sdst_5>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_buffer_store_dword                     :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_store_dwordx2                   :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_buffer_store_dwordx4                   :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_1>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_2>`        :ref:`glc<amdgpu_synid_glc>`
    s_dcache_discard                         :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
    s_dcache_discard_x2                      :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`
    s_dcache_inv
    s_dcache_wb
    s_get_waveid_in_workgroup      :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`
    s_gl1_inv
    s_load_dword                   :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_load_dwordx16                :ref:`sdst<amdgpu_synid_gfx10_sdst_2>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_load_dwordx2                 :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_load_dwordx4                 :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_load_dwordx8                 :ref:`sdst<amdgpu_synid_gfx10_sdst_5>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_memrealtime                  :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
    s_memtime                      :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`::ref:`b64<amdgpu_synid_gfx10_type_deviation>`
    s_scratch_load_dword           :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_scratch_load_dwordx2         :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_scratch_load_dwordx4         :ref:`sdst<amdgpu_synid_gfx10_sdst_4>`,     :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,           :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`                  :ref:`glc<amdgpu_synid_glc>` :ref:`dlc<amdgpu_synid_dlc>`
    s_scratch_store_dword                    :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_scratch_store_dwordx2                  :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_scratch_store_dwordx4                  :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase_2>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_store_dword                            :ref:`sdata<amdgpu_synid_gfx10_sdata_3>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_store_dwordx2                          :ref:`sdata<amdgpu_synid_gfx10_sdata_4>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`
    s_store_dwordx4                          :ref:`sdata<amdgpu_synid_gfx10_sdata_5>`,           :ref:`sbase<amdgpu_synid_gfx10_sbase>`,    :ref:`soffset<amdgpu_synid_gfx10_soffset_1>`        :ref:`glc<amdgpu_synid_glc>`

SOP1
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_abs_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_and_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_and_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_andn1_saveexec_b32           :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_andn1_saveexec_b64           :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_andn1_wrexec_b32             :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_andn1_wrexec_b64             :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_andn2_saveexec_b32           :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_andn2_saveexec_b64           :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_andn2_wrexec_b32             :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_andn2_wrexec_b64             :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_bcnt0_i32_b32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_bcnt0_i32_b64                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_bcnt1_i32_b32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_bcnt1_i32_b64                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_bitreplicate_b64_b32         :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_bitset0_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_bitset0_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    s_bitset1_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_bitset1_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    s_brev_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_brev_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_cmov_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_cmov_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_ff0_i32_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_ff0_i32_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_ff1_i32_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_ff1_i32_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_flbit_i32                    :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_flbit_i32_b32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_flbit_i32_b64                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_flbit_i32_i64                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_getpc_b64                    :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`
    s_mov_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_mov_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_movreld_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_movreld_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_movrels_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2>`
    s_movrels_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
    s_movrelsd_2_b32               :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_2>`
    s_nand_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_nand_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_nor_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_nor_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_not_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_not_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_or_saveexec_b32              :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_or_saveexec_b64              :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_orn1_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_orn1_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_orn2_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_orn2_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_quadmask_b32                 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_quadmask_b64                 :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_rfe_b64                                :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
    s_setpc_b64                              :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
    s_sext_i32_i16                 :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_sext_i32_i8                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_swappc_b64                   :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_3>`
    s_wqm_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_wqm_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_xnor_saveexec_b32            :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_xnor_saveexec_b64            :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`
    s_xor_saveexec_b32             :ref:`sdst<amdgpu_synid_gfx10_sdst_1>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc>`
    s_xor_saveexec_b64             :ref:`sdst<amdgpu_synid_gfx10_sdst_3>`,     :ref:`ssrc<amdgpu_synid_gfx10_ssrc_1>`

SOP2
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_absdiff_i32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_add_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_add_u32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_addc_u32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_and_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_and_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_andn2_b32                    :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_andn2_b64                    :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_ashr_i32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_ashr_i64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_bfe_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_bfe_i64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_bfe_u32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_bfe_u64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_bfm_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_bfm_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    s_cselect_b32                  :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cselect_b64                  :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_lshl1_add_u32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_lshl2_add_u32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_lshl3_add_u32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_lshl4_add_u32                :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_lshl_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_lshl_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_lshr_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_lshr_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_max_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_max_u32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_min_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_min_u32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_mul_hi_i32                   :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_mul_hi_u32                   :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_mul_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_nand_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_nand_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_nor_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_nor_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_or_b32                       :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_or_b64                       :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_orn2_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_orn2_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_pack_hh_b32_b16              :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    s_pack_lh_b32_b16              :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    s_pack_ll_b32_b16              :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_sub_i32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_sub_u32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_subb_u32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_xnor_b32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_xnor_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_xor_b32                      :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_xor_b64                      :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,     :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`

SOPC
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **SRC0**      **SRC1**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_bitcmp0_b32                  :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_bitcmp0_b64                  :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_bitcmp1_b32                  :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_bitcmp1_b64                  :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    s_cmp_eq_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_eq_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_eq_u64                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_cmp_ge_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_ge_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_gt_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_gt_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_le_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_le_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_lg_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_lg_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_lg_u64                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_1>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_1>`
    s_cmp_lt_i32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`
    s_cmp_lt_u32                   :ref:`ssrc0<amdgpu_synid_gfx10_ssrc>`,    :ref:`ssrc1<amdgpu_synid_gfx10_ssrc>`

SOPK
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_addk_i32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_call_b64                     :ref:`sdst<amdgpu_synid_gfx10_sdst_7>`,     :ref:`label<amdgpu_synid_gfx10_label>`
    s_cmovk_i32                    :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_eq_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_eq_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_cmpk_ge_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_ge_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_cmpk_gt_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_gt_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_cmpk_le_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_le_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_cmpk_lg_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_lg_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_cmpk_lt_i32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_cmpk_lt_u32                            :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_1>`
    s_getreg_b32                   :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`
    s_movk_i32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_mulk_i32                     :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16>`
    s_setreg_b32                   :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`,    :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`
    s_setreg_imm32_b32             :ref:`hwreg<amdgpu_synid_gfx10_hwreg>`,    :ref:`simm32<amdgpu_synid_gfx10_simm32>`
    s_subvector_loop_begin         :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`label<amdgpu_synid_gfx10_label>`
    s_subvector_loop_end           :ref:`sdst<amdgpu_synid_gfx10_sdst_6>`,     :ref:`label<amdgpu_synid_gfx10_label>`
    s_version                                :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_waitcnt_expcnt                         :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_waitcnt_lgkmcnt                        :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_waitcnt_vmcnt                          :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_waitcnt_vscnt                          :ref:`ssrc<amdgpu_synid_gfx10_ssrc_4>`,     :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`

SOPP
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **SRC**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    s_barrier
    s_branch                       :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_cdbgsys              :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_cdbgsys_and_user     :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_cdbgsys_or_user      :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_cdbguser             :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_execnz               :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_execz                :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_scc0                 :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_scc1                 :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_vccnz                :ref:`label<amdgpu_synid_gfx10_label>`
    s_cbranch_vccz                 :ref:`label<amdgpu_synid_gfx10_label>`
    s_clause                       :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_code_end
    s_decperflevel                 :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_denorm_mode                  :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_endpgm
    s_endpgm_ordered_ps_done
    s_endpgm_saved
    s_icache_inv
    s_incperflevel                 :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_inst_prefetch                :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_nop                          :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_round_mode                   :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_sendmsg                      :ref:`msg<amdgpu_synid_gfx10_msg>`
    s_sendmsghalt                  :ref:`msg<amdgpu_synid_gfx10_msg>`
    s_sethalt                      :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_setkill                      :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_setprio                      :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_sleep                        :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_trap                         :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_ttracedata
    s_ttracedata_imm               :ref:`imm16<amdgpu_synid_gfx10_imm16_2>`
    s_waitcnt                      :ref:`waitcnt<amdgpu_synid_gfx10_waitcnt>`
    s_wakeup

VINTRP
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_interp_mov_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_interp_p1_f32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`,      :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_interp_p2_f32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`,      :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`

VOP1
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**        **SRC**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_bfrev_b32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ceil_f16                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ceil_f32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ceil_f64                     :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_clrexcp
    v_cos_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cos_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_4>`
    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_4>`
    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_cvt_norm_i16_f16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_norm_u16_f16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_exp_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_exp_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ffbh_i32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ffbh_u32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ffbl_b32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_floor_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_floor_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_floor_f64                    :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_fract_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_fract_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_fract_f64                    :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_frexp_mant_f64               :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_log_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_log_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_mov_b32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_movreld_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_movrels_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_movrelsd_2_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_movrelsd_b32                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_nop
    v_not_b32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_pipeflush
    v_rcp_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rcp_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rcp_f64                      :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_readfirstlane_b32            :ref:`sdst<amdgpu_synid_gfx10_sdst_8>`,      :ref:`src<amdgpu_synid_gfx10_src_5>`
    v_rndne_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rndne_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rndne_f64                    :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_rsq_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rsq_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_rsq_f64                      :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_sat_pk_u8_i16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`, :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sin_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sin_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sqrt_f16                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sqrt_f32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sqrt_f64                     :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`
    v_swap_b32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_swaprel_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_trunc_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_trunc_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,      :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_trunc_f64                    :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,      :ref:`src<amdgpu_synid_gfx10_src_3>`

VOP2
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST0**      **DST1**      **SRC0**      **SRC1**      **SRC2**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_add_co_ci_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`
    v_add_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_add_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_add_nc_u32                   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_and_b32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cndmask_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`
    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
    v_fmaak_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`simm32<amdgpu_synid_gfx10_simm32_1>`
    v_fmaak_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`
    v_fmac_f16                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_fmac_f32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_fmamk_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`simm32<amdgpu_synid_gfx10_simm32_1>`,   :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
    v_fmamk_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`,   :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
    v_ldexp_f16                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`
    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`, :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mac_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mac_legacy_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_madak_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`
    v_madmk_f32                    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_7>`,     :ref:`simm32<amdgpu_synid_gfx10_simm32_2>`,   :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`
    v_max_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_max_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_max_i32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_max_u32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_min_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_min_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_min_i32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_min_u32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_or_b32                       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_pk_fmac_f16                  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_sub_co_ci_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`
    v_sub_f16                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_sub_f32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_sub_nc_u32                   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_subrev_co_ci_u32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,     :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_6>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`,    :ref:`vcc<amdgpu_synid_gfx10_vcc>`
    v_subrev_f16                   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_subrev_f32                   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_subrev_nc_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_6>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_xnor_b32                     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_xor_b32                      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,               :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`

VOP3
-----------------------

.. parsed-literal::

    **INSTRUCTION**              **DST0**        **DST1**     **SRC0**         **SRC1**        **SRC2**           **MODIFIERS**
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    v_add3_u32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_add_co_ci_u32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>`          :ref:`clamp<amdgpu_synid_clamp>`
    v_add_co_u32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_add_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_add_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_add_f64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_add_lshl_u32           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_add_nc_i16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`                       :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_add_nc_i32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_add_nc_u16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_add_nc_u32_e64         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_alignbit_b32           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
    v_alignbyte_b32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`::ref:`b16<amdgpu_synid_gfx10_type_deviation>`
    v_and_b32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_and_or_b32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_ashrrev_i16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_ashrrev_i32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_ashrrev_i64            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_bcnt_u32_b32           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_bfe_i32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    v_bfe_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_bfi_b32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_bfm_b32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_bfrev_b32_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ceil_f16_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ceil_f32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ceil_f64_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_clrexcp_e64
    v_cmp_class_f16_e64      :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_class_f32_e64      :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_class_f64_e64      :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_eq_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_eq_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_eq_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_eq_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_eq_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_eq_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_eq_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_eq_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_eq_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_f_f16_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_f_f32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_f_f64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_f_i32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_f_i64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_f_u32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_f_u64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_ge_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ge_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ge_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ge_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_ge_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_ge_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_ge_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_ge_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_ge_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_gt_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_gt_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_gt_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_gt_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_gt_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_gt_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_gt_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_gt_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_gt_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_le_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_le_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_le_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_le_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_le_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_le_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_le_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_le_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_le_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_lg_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lg_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lg_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lt_f16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lt_f32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lt_f64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_lt_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_lt_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_lt_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_lt_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_lt_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_lt_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_ne_i16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_ne_i32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_ne_i64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_ne_u16_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmp_ne_u32_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_ne_u64_e64         :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_neq_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_neq_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_neq_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nge_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nge_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nge_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ngt_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ngt_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_ngt_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nle_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nle_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nle_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlg_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlg_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlg_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlt_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlt_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_nlt_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_o_f16_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_o_f32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_o_f64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_t_i32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_t_i64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_t_u32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmp_t_u64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmp_tru_f16_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_tru_f32_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_tru_f64_e64        :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_u_f16_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_u_f32_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmp_u_f64_e64          :ref:`sdst<amdgpu_synid_gfx10_sdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_class_f16_e64                          :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_class_f32_e64                          :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_class_f64_e64                          :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_eq_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_eq_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_eq_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_eq_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_eq_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_eq_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_eq_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_eq_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_eq_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_f_f16_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_f_f32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_f_f64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_f_i32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_f_i64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_f_u32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_f_u64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_ge_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ge_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ge_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ge_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_ge_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_ge_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_ge_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_ge_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_ge_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_gt_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_gt_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_gt_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_gt_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_gt_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_gt_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_gt_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_gt_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_gt_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_le_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_le_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_le_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_le_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_le_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_le_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_le_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_le_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_le_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_lg_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lg_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lg_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lt_f16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lt_f32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lt_f64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_lt_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_lt_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_lt_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_lt_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_lt_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_lt_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_ne_i16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_ne_i32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_ne_i64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_ne_u16_e64                             :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_cmpx_ne_u32_e64                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_ne_u64_e64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_neq_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_neq_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_neq_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nge_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nge_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nge_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ngt_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ngt_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_ngt_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nle_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nle_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nle_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlg_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlg_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlg_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlt_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlt_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_nlt_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_o_f16_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_o_f32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_o_f64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_t_i32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_t_i64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_t_u32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_cmpx_t_u64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_cmpx_tru_f16_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_tru_f32_e64                            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_tru_f64_e64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_u_f16_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_u_f32_e64                              :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cmpx_u_f64_e64                              :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>`
    v_cndmask_b32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>`
    v_cos_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cos_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cubeid_f32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cubema_f32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cubesc_f32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cubetc_f32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f16_f32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f16_i16_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_4>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f16_u16_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_4>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_f16_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_f64_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_i32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_u32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_ubyte0_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_ubyte1_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_ubyte2_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f32_ubyte3_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f64_f32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f64_i32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_f64_u32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_flr_i32_f32_e64    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
    v_cvt_i16_f16_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_i32_f32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_i32_f64_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_norm_i16_f16_e64   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_norm_u16_f16_e64   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_off_f32_i4_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`                                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_cvt_pk_i16_i32         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`
    v_cvt_pk_u16_u32         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    v_cvt_pk_u8_f32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`
    v_cvt_pknorm_i16_f16     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`                 :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_cvt_pknorm_i16_f32     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
    v_cvt_pknorm_u16_f16     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16<amdgpu_synid_gfx10_type_deviation>`                 :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_cvt_pknorm_u16_f32     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`
    v_cvt_pkrtz_f16_f32_e64  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`                 :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_rpi_i32_f32_e64    :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
    v_cvt_u16_f16_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_u32_f32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_cvt_u32_f64_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>`
    v_div_fixup_f16          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_div_fixup_f32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_div_fixup_f64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_div_fmas_f32           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_div_fmas_f64           :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_div_scale_f32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`vcc<amdgpu_synid_gfx10_vcc>`,     :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_div_scale_f64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`vcc<amdgpu_synid_gfx10_vcc>`,     :ref:`src0<amdgpu_synid_gfx10_src_3>`,        :ref:`src1<amdgpu_synid_gfx10_src_3>`,       :ref:`src2<amdgpu_synid_gfx10_src_3>`
    v_exp_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_exp_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ffbh_i32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ffbh_u32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_ffbl_b32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_floor_f16_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_floor_f32_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_floor_f64_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fma_f16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_fma_f32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fma_f64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fmac_f16_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fmac_f32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fract_f16_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fract_f32_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_fract_f64_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_frexp_exp_i16_f16_e64  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
    v_frexp_exp_i32_f32_e64  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`
    v_frexp_exp_i32_f64_e64  :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`
    v_frexp_mant_f16_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_frexp_mant_f32_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_frexp_mant_f64_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_interp_mov_f32_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`param<amdgpu_synid_gfx10_param>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_interp_p1_f32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_interp_p1ll_f16        :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,  :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_interp_p1lv_f16        :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f16x2<amdgpu_synid_gfx10_type_deviation>`  :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_interp_p2_f16          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc0<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`, :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`vsrc2<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`f32<amdgpu_synid_gfx10_type_deviation>`    :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
    v_interp_p2_f32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`attr<amdgpu_synid_gfx10_attr>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ldexp_f16_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i16<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ldexp_f32              :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_ldexp_f64              :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_lerp_u8                :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_log_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_log_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_lshl_add_u32           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_lshl_or_b32            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_lshlrev_b16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_lshlrev_b32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_lshlrev_b64            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_lshrrev_b16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_lshrrev_b32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_lshrrev_b64            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_3>`
    v_mac_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mac_legacy_f32_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mad_f32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mad_i16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_i32_i16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`       :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_i32_i24            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`i32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_i64_i32            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`i64<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_legacy_f32         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mad_u16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_u32_u16            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`       :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_u32_u24            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_mad_u64_u32            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u64<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_max3_f16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_max3_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_max3_i16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_max3_i32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_max3_u16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_max3_u32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_max_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_max_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_max_f64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_max_i16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_max_i32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_max_u16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_max_u32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mbcnt_hi_u32_b32       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mbcnt_lo_u32_b32       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_med3_f16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_med3_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_med3_i16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_med3_i32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_med3_u16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_med3_u32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_min3_f16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_min3_f32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_min3_i16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_min3_i32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_min3_u16               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`,       :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_min3_u32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_min_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_min_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_min_f64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_min_i16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_min_i32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_min_u16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_min_u32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mov_b32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_movreld_b32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_movrels_b32_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_movrelsd_2_b32_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_movrelsd_b32_e64       :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vsrc<amdgpu_synid_gfx10_vsrc>`
    v_mqsad_pk_u16_u8        :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`,          :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`     :ref:`clamp<amdgpu_synid_clamp>`
    v_mqsad_u32_u8           :ref:`vdst<amdgpu_synid_gfx10_vdst_2>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>`,          :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,  :ref:`vsrc2<amdgpu_synid_gfx10_vsrc_2>`::ref:`u32x4<amdgpu_synid_gfx10_type_deviation>`    :ref:`clamp<amdgpu_synid_clamp>`
    v_msad_u8                :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,    :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_mul_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mul_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mul_f64                :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mul_hi_i32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mul_hi_i32_i24_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mul_hi_u32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mul_hi_u32_u24_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mul_i32_i24_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_mul_legacy_f32_e64     :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_mul_lo_u16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`
    v_mul_lo_u32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_mul_u32_u24_e64        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_mullit_f32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,     :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_nop_e64
    v_not_b32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_or3_b32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_or_b32_e64             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_pack_b32_f16           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
    v_perm_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_permlane16_b32         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_6>`,      :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_6>`          :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
    v_permlanex16_b32        :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`vdata<amdgpu_synid_gfx10_vdata>`,       :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_6>`,      :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_6>`          :ref:`dpp_op_sel<amdgpu_synid_dpp_op_sel>`
    v_pipeflush_e64
    v_qsad_pk_u16_u8         :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`,          :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`u8x8<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src2<amdgpu_synid_gfx10_src_3>`::ref:`u16x4<amdgpu_synid_gfx10_type_deviation>`     :ref:`clamp<amdgpu_synid_clamp>`
    v_rcp_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rcp_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rcp_f64_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rcp_iflag_f32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_readlane_b32           :ref:`sdst<amdgpu_synid_gfx10_sdst_8>`,                :ref:`src0<amdgpu_synid_gfx10_src_5>`,        :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7>`
    v_rndne_f16_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rndne_f32_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rndne_f64_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rsq_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rsq_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_rsq_f64_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sad_hi_u8              :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_sad_u16                :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_sad_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`           :ref:`clamp<amdgpu_synid_clamp>`
    v_sad_u8                 :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`,            :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,   :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,  :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`       :ref:`clamp<amdgpu_synid_clamp>`
    v_sat_pk_u8_i16_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`::ref:`u8x4<amdgpu_synid_gfx10_type_deviation>`,           :ref:`src<amdgpu_synid_gfx10_src_2>`
    v_sin_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sin_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sqrt_f16_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sqrt_f32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sqrt_f64_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sub_co_ci_u32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>`          :ref:`clamp<amdgpu_synid_clamp>`
    v_sub_co_u32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_sub_f16_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sub_f32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_sub_nc_i16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`                       :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
    v_sub_nc_i32             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_sub_nc_u16             :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_4>`,        :ref:`src1<amdgpu_synid_gfx10_src_8>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_sub_nc_u32_e64         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_subrev_co_ci_u32_e64   :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_6>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`ssrc2<amdgpu_synid_gfx10_ssrc_5>`          :ref:`clamp<amdgpu_synid_clamp>`
    v_subrev_co_u32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,       :ref:`sdst<amdgpu_synid_gfx10_sdst>`,    :ref:`src0<amdgpu_synid_gfx10_src_6>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_subrev_f16_e64         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_subrev_f32_e64         :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`                     :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_subrev_nc_u32_e64      :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_6>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`                       :ref:`clamp<amdgpu_synid_clamp>`
    v_trig_preop_f64         :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src0<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`,      :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`u32<amdgpu_synid_gfx10_type_deviation>`                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_trunc_f16_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_trunc_f32_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_trunc_f64_e64          :ref:`vdst<amdgpu_synid_gfx10_vdst_1>`,                :ref:`src<amdgpu_synid_gfx10_src_3>`::ref:`m<amdgpu_synid_gfx10_m>`                                   :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
    v_writelane_b32          :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`ssrc0<amdgpu_synid_gfx10_ssrc_8>`,       :ref:`ssrc1<amdgpu_synid_gfx10_ssrc_7>`
    v_xad_u32                :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_xnor_b32_e64           :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`
    v_xor3_b32               :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`,       :ref:`src2<amdgpu_synid_gfx10_src_6>`
    v_xor_b32_e64            :ref:`vdst<amdgpu_synid_gfx10_vdst>`,                :ref:`src0<amdgpu_synid_gfx10_src_2>`,        :ref:`src1<amdgpu_synid_gfx10_src_6>`

VOP3P
-----------------------

.. parsed-literal::

    **INSTRUCTION**          **DST**   **SRC0**        **SRC1**       **SRC2**           **MODIFIERS**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_fma_mix_f32        :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`      :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_fma_mixhi_f16      :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`      :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_fma_mixlo_f16      :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`,  :ref:`src1<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`, :ref:`src2<amdgpu_synid_gfx10_src_6>`::ref:`m<amdgpu_synid_gfx10_m>`::ref:`fx<amdgpu_synid_gfx10_fx_operand>`      :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_add_f16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`,       :ref:`src1<amdgpu_synid_gfx10_src_6>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_add_i16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_add_u16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_ashrrev_i16     :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_fma_f16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`,       :ref:`src1<amdgpu_synid_gfx10_src_6>`,      :ref:`src2<amdgpu_synid_gfx10_src_6>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_lshlrev_b16     :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_lshrrev_b16     :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_8>`::ref:`u16x2<amdgpu_synid_gfx10_type_deviation>`, :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_mad_i16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`,      :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_mad_u16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`,      :ref:`src2<amdgpu_synid_gfx10_src_8>`           :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_max_f16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`,       :ref:`src1<amdgpu_synid_gfx10_src_6>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_max_i16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_max_u16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_min_f16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`,       :ref:`src1<amdgpu_synid_gfx10_src_6>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_min_i16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_min_u16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_mul_f16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_2>`,       :ref:`src1<amdgpu_synid_gfx10_src_6>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_mul_lo_u16      :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
    v_pk_sub_i16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
    v_pk_sub_u16         :ref:`vdst<amdgpu_synid_gfx10_vdst>`, :ref:`src0<amdgpu_synid_gfx10_src_4>`,       :ref:`src1<amdgpu_synid_gfx10_src_8>`                      :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`

VOPC
-----------------------

.. parsed-literal::

    **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
    v_cmp_class_f16                :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_class_f32                :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_class_f64                :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_f_f64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_f_i64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_f_u64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_le_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_o_f64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_t_i64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_t_u64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmp_u_f64                    :ref:`vcc<amdgpu_synid_gfx10_vcc>`,      :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_class_f16                         :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_class_f32                         :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_class_f64                         :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`::ref:`b32<amdgpu_synid_gfx10_type_deviation>`
    v_cmpx_eq_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_eq_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_eq_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_eq_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_f_f16                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_f_f32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_f_f64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_f_i32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_f_i64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_f_u32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_f_u64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ge_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ge_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ge_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ge_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_gt_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_gt_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_gt_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_gt_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_le_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_le_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_le_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_le_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_lg_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lg_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lg_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_lt_f16                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_f32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_f64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_lt_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_lt_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_lt_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ne_i16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ne_i32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ne_i64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ne_u16                            :ref:`src0<amdgpu_synid_gfx10_src_4>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ne_u32                            :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ne_u64                            :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_neq_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_neq_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_neq_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_nge_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nge_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nge_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_ngt_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ngt_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_ngt_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_nle_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nle_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nle_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_nlg_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nlg_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nlg_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_nlt_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nlt_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_nlt_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_o_f16                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_o_f32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_o_f64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_t_i32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_t_i64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_t_u32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_t_u64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_tru_f16                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_tru_f32                           :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_tru_f64                           :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`
    v_cmpx_u_f16                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_u_f32                             :ref:`src0<amdgpu_synid_gfx10_src_2>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc>`
    v_cmpx_u_f64                             :ref:`src0<amdgpu_synid_gfx10_src_3>`,     :ref:`vsrc1<amdgpu_synid_gfx10_vsrc_3>`

.. |---| unicode:: U+02014 .. em dash

.. toctree::
    :hidden:

    gfx10_attr
    gfx10_dst
    gfx10_fx_operand
    gfx10_hwreg
    gfx10_imm16
    gfx10_imm16_1
    gfx10_imm16_2
    gfx10_label
    gfx10_m
    gfx10_m_1
    gfx10_msg
    gfx10_opt
    gfx10_param
    gfx10_probe
    gfx10_saddr
    gfx10_saddr_1
    gfx10_sbase
    gfx10_sbase_1
    gfx10_sbase_2
    gfx10_sdata
    gfx10_sdata_1
    gfx10_sdata_2
    gfx10_sdata_3
    gfx10_sdata_4
    gfx10_sdata_5
    gfx10_sdst
    gfx10_sdst_1
    gfx10_sdst_2
    gfx10_sdst_3
    gfx10_sdst_4
    gfx10_sdst_5
    gfx10_sdst_6
    gfx10_sdst_7
    gfx10_sdst_8
    gfx10_simm32
    gfx10_simm32_1
    gfx10_simm32_2
    gfx10_soffset
    gfx10_soffset_1
    gfx10_soffset_2
    gfx10_src
    gfx10_src_1
    gfx10_src_2
    gfx10_src_3
    gfx10_src_4
    gfx10_src_5
    gfx10_src_6
    gfx10_src_7
    gfx10_src_8
    gfx10_srsrc
    gfx10_srsrc_1
    gfx10_ssamp
    gfx10_ssrc
    gfx10_ssrc_1
    gfx10_ssrc_2
    gfx10_ssrc_3
    gfx10_ssrc_4
    gfx10_ssrc_5
    gfx10_ssrc_6
    gfx10_ssrc_7
    gfx10_ssrc_8
    gfx10_tgt
    gfx10_type_deviation
    gfx10_vaddr
    gfx10_vaddr_1
    gfx10_vaddr_2
    gfx10_vaddr_3
    gfx10_vaddr_4
    gfx10_vaddr_5
    gfx10_vcc
    gfx10_vdata
    gfx10_vdata0
    gfx10_vdata0_1
    gfx10_vdata1
    gfx10_vdata1_1
    gfx10_vdata_1
    gfx10_vdata_10
    gfx10_vdata_2
    gfx10_vdata_3
    gfx10_vdata_4
    gfx10_vdata_5
    gfx10_vdata_6
    gfx10_vdata_7
    gfx10_vdata_8
    gfx10_vdata_9
    gfx10_vdst
    gfx10_vdst_1
    gfx10_vdst_10
    gfx10_vdst_11
    gfx10_vdst_12
    gfx10_vdst_13
    gfx10_vdst_2
    gfx10_vdst_3
    gfx10_vdst_4
    gfx10_vdst_5
    gfx10_vdst_6
    gfx10_vdst_7
    gfx10_vdst_8
    gfx10_vdst_9
    gfx10_vsrc
    gfx10_vsrc_1
    gfx10_vsrc_2
    gfx10_vsrc_3
    gfx10_waitcnt