commit 7a753d9bec529698c16475c72cf1de386b63381f
author Tim Northover <tnorthover@apple.com> Fri Aug 26 17:46:06 2016 +0000
committer Tim Northover <tnorthover@apple.com> Fri Aug 26 17:46:06 2016 +0000
tree bd0f2ee6bfa04c1e7d4788f14bfbefcb130e85fb
parent 1d18a99a53a3a37ccffdf36341da2d46c8f6c201

GlobalISel: legalize under-width divisions.

llvm-svn: 279841

llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
index 66b7166..401f29a 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -161,6 +161,33 @@
     MI.eraseFromParent();
     return Legalized;
   }
+  case TargetOpcode::G_SDIV:
+  case TargetOpcode::G_UDIV: {
+    unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV
+                          ? TargetOpcode::G_SEXT
+                          : TargetOpcode::G_ZEXT;
+
+    unsigned LHSExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildInstr(ExtOp, {WideTy, MI.getType()})
+        .addDef(LHSExt)
+        .addUse(MI.getOperand(1).getReg());
+
+    unsigned RHSExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildInstr(ExtOp, {WideTy, MI.getType()})
+        .addDef(RHSExt)
+        .addUse(MI.getOperand(2).getReg());
+
+    unsigned ResExt = MRI.createGenericVirtualRegister(WideSize);
+    MIRBuilder.buildInstr(MI.getOpcode(), WideTy)
+        .addDef(ResExt)
+        .addUse(LHSExt)
+        .addUse(RHSExt);
+
+    MIRBuilder.buildTrunc({MI.getType(), WideTy}, MI.getOperand(0).getReg(),
+                          ResExt);
+    MI.eraseFromParent();
+    return Legalized;
+  }
   case TargetOpcode::G_LOAD: {
     assert(alignTo(Ty.getSizeInBits(), 8) == WideSize &&
            "illegal to increase number of bytes loaded");