| commit | 7a424276dee30154ec84b7494ef6040e10684a4e | [log] [tgz] |
|---|---|---|
| author | Feng Zou <feng.zou@intel.com> | Fri Apr 25 10:55:31 2025 +0800 |
| committer | GitHub <noreply@github.com> | Fri Apr 25 10:55:31 2025 +0800 |
| tree | d7691dd7ecd7f53e07dc11029c7b5b78e3e2a6b0 | |
| parent | fb01f19f3cf6b3317983b06a7dbf5ed143072990 [diff] |
Revert "[X86][APX] Support peephole optimization with CCMP instruction (#129994)" (#136796)
This reverts commit 7ae75851b2e1570662261c97c13cfc65357c283d.
There is a problem with peephole optimization for CCMP instruction. See
the example below:
C source code:
```
if (a > 2 || (b && (a == 2))) { … }
```
MIR before peephole optimization:
```
TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b
CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2
CCMP32ri %30:gr32, 3, 0, 5, implicit-def $eflags, implicit $eflags // a > 2 (transformed to a < 3)
JCC_1 %bb.6, 2, implicit $eflags
JMP_1 %bb.3
```
Inputs:
```
a = 1, b = 0.
```
With the inputs above, the expected behavior is to jump to %bb.6 BB.
After TEST8rr instruction being executed with b(%21) == 0, the ZF bit is
set to 1 in eflags, so the eflags doesn't satisfy SCC condition in the
following CCMP32ri instruction (for a==2 condition) which skips compare
a(%30) with 2 and set flags in its payload to 0x202 (ZF = 0). The eflags
satisfies the SCC condition in the 2nd CCMP32ri instruction which
compares a(%30) with 3. It sets CF to 1 in eflags and the JCC
instruction jumps to %bb.6 BB.
But after adding CCMP support, peephole optimization eliminates the 2nd
CCMP32ri instruction and updates the condition of JCC instruction to
"BE" from "B". With the same inputs, JCC instruction falls through to
the next instruction. It's not expected and the 2nd CCMP32ri should not
be eliminated.
```
TEST8rr %21:gr8, %21:gr8, implicit-def $eflags // b
CCMP32ri %30:gr32, 2, 0, 5, implicit-def $eflags, implicit $eflags // a == 2
JCC_1 %bb.6, 6, implicit $eflags
JMP_1 %bb.3
```
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