| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK2 |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK4 |
| |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DLAMBDA -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DLAMBDA -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK9 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK10 |
| // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK11 |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --check-prefix=CHECK12 |
| |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - -Wno-openmp-mapping | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| |
| template <class T> |
| struct S { |
| T f; |
| S(T a) : f(a) {} |
| S() : f() {} |
| operator T() { return T(); } |
| ~S() {} |
| }; |
| |
| template <typename T> |
| T tmain() { |
| S<T> test; |
| T t_var = T(); |
| T vec[] = {1, 2}; |
| S<T> s_arr[] = {1, 2}; |
| S<T> &var = test; |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute firstprivate(t_var, vec, s_arr, s_arr, var, var) |
| for (int i = 0; i < 2; ++i) { |
| vec[i] = t_var; |
| s_arr[i] = var; |
| } |
| return T(); |
| } |
| |
| int main() { |
| static int svar; |
| volatile double g; |
| volatile double &g1 = g; |
| |
| #ifdef LAMBDA |
| [&]() { |
| static float sfvar; |
| |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute firstprivate(g, g1, svar, sfvar) |
| for (int i = 0; i < 2; ++i) { |
| // Private alloca's for conversion |
| |
| // Actual private variables to be used in the body (tmp is used for the reference type) |
| |
| // Store input parameter addresses into private alloca's for conversion |
| |
| g += 1; |
| g1 += 1; |
| svar += 3; |
| sfvar += 4.0; |
| |
| // call inner lambda (use refs to private alloca's) |
| [&]() { |
| g += 2; |
| g1 += 2; |
| svar += 4; |
| sfvar += 8.0; |
| |
| |
| |
| }(); |
| } |
| }(); |
| return 0; |
| #else |
| S<float> test; |
| int t_var = 0; |
| int vec[] = {1, 2}; |
| S<float> s_arr[] = {1, 2}; |
| S<float> &var = test; |
| |
| #pragma omp target |
| #pragma omp teams |
| #pragma omp distribute firstprivate(t_var, vec, s_arr, s_arr, var, var, svar) |
| for (int i = 0; i < 2; ++i) { |
| vec[i] = t_var; |
| s_arr[i] = var; |
| } |
| return tmain<int>(); |
| #endif |
| } |
| |
| |
| |
| |
| // discard omp loop variables |
| |
| |
| |
| // init t_var |
| |
| // init vec |
| |
| // init s_arr |
| |
| |
| // init var |
| |
| // init svar |
| |
| |
| |
| // Template |
| |
| |
| |
| // discard omp loop variables |
| |
| |
| |
| // init t_var |
| |
| // init vec |
| |
| // init s_arr |
| |
| |
| // init var |
| |
| |
| #endif |
| // CHECK1-LABEL: define {{[^@]+}}@main |
| // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[G1:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK1-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK1-NEXT: store double* [[G]], double** [[G1]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 |
| // CHECK1-NEXT: store double* [[G]], double** [[TMP0]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 |
| // CHECK1-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 |
| // CHECK1-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) |
| // CHECK1-NEXT: ret i32 0 |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK1-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to double* |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to double* |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* |
| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* |
| // CHECK1-NEXT: store double* [[CONV1]], double** [[TMP]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, double*, i32*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[CONV]], double* [[TMP0]], i32* [[CONV2]], float* [[CONV3]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[SFVAR_ADDR:%.*]] = alloca float*, align 8 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[_TMP1:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK1-NEXT: [[_TMP5:%.*]] = alloca double*, align 8 |
| // CHECK1-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store double* [[G]], double** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store float* [[SFVAR]], float** [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load float*, float** [[SFVAR_ADDR]], align 8 |
| // CHECK1-NEXT: store double* [[TMP1]], double** [[TMP]], align 8 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 8 |
| // CHECK1-NEXT: store double* [[TMP4]], double** [[_TMP1]], align 8 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load volatile double, double* [[TMP0]], align 8 |
| // CHECK1-NEXT: store double [[TMP5]], double* [[G3]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[_TMP1]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load volatile double, double* [[TMP6]], align 8 |
| // CHECK1-NEXT: store double [[TMP7]], double* [[G14]], align 8 |
| // CHECK1-NEXT: store double* [[G14]], double** [[_TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP2]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP8]], i32* [[SVAR6]], align 4 |
| // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[TMP3]], align 4 |
| // CHECK1-NEXT: store float [[TMP9]], float* [[SFVAR7]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 |
| // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] |
| // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 |
| // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 |
| // CHECK1-NEXT: store double [[ADD9]], double* [[G3]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8 |
| // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 |
| // CHECK1-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8 |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 |
| // CHECK1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 |
| // CHECK1-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double |
| // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 |
| // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float |
| // CHECK1-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 |
| // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 |
| // CHECK1-NEXT: store double* [[G3]], double** [[TMP23]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 |
| // CHECK1-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8 |
| // CHECK1-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 |
| // CHECK1-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 |
| // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 |
| // CHECK1-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 |
| // CHECK1-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 |
| // CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK1-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@main |
| // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK2-NEXT: [[G1:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 8 |
| // CHECK2-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK2-NEXT: store double* [[G]], double** [[G1]], align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 |
| // CHECK2-NEXT: store double* [[G]], double** [[TMP0]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 8 |
| // CHECK2-NEXT: store double* [[TMP2]], double** [[TMP1]], align 8 |
| // CHECK2-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 8 dereferenceable(16) [[REF_TMP]]) |
| // CHECK2-NEXT: ret i32 0 |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK2-SAME: (i64 [[G:%.*]], i64 [[G1:%.*]], i64 [[SVAR:%.*]], i64 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[SFVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: store i64 [[G]], i64* [[G_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[G1]], i64* [[G1_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[SFVAR]], i64* [[SFVAR_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[G_ADDR]] to double* |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[G1_ADDR]] to double* |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* |
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[SFVAR_ADDR]] to float* |
| // CHECK2-NEXT: store double* [[CONV1]], double** [[TMP]], align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[TMP]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, double*, i32*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[CONV]], double* [[TMP0]], i32* [[CONV2]], float* [[CONV3]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 8 dereferenceable(8) [[G:%.*]], double* nonnull align 8 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[SFVAR_ADDR:%.*]] = alloca float*, align 8 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[_TMP1:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK2-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK2-NEXT: [[_TMP5:%.*]] = alloca double*, align 8 |
| // CHECK2-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store double* [[G]], double** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 |
| // CHECK2-NEXT: store float* [[SFVAR]], float** [[SFVAR_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load float*, float** [[SFVAR_ADDR]], align 8 |
| // CHECK2-NEXT: store double* [[TMP1]], double** [[TMP]], align 8 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 8 |
| // CHECK2-NEXT: store double* [[TMP4]], double** [[_TMP1]], align 8 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load volatile double, double* [[TMP0]], align 8 |
| // CHECK2-NEXT: store double [[TMP5]], double* [[G3]], align 8 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[_TMP1]], align 8 |
| // CHECK2-NEXT: [[TMP7:%.*]] = load volatile double, double* [[TMP6]], align 8 |
| // CHECK2-NEXT: store double [[TMP7]], double* [[G14]], align 8 |
| // CHECK2-NEXT: store double* [[G14]], double** [[_TMP5]], align 8 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP2]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP8]], i32* [[SVAR6]], align 4 |
| // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[TMP3]], align 4 |
| // CHECK2-NEXT: store float [[TMP9]], float* [[SFVAR7]], align 4 |
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 |
| // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK2: cond.true: |
| // CHECK2-NEXT: br label [[COND_END:%.*]] |
| // CHECK2: cond.false: |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: br label [[COND_END]] |
| // CHECK2: cond.end: |
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] |
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK2: omp.inner.for.cond: |
| // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] |
| // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK2: omp.inner.for.body: |
| // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK2-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 |
| // CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 |
| // CHECK2-NEXT: store double [[ADD9]], double* [[G3]], align 8 |
| // CHECK2-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 8 |
| // CHECK2-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 8 |
| // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 |
| // CHECK2-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 8 |
| // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 |
| // CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 |
| // CHECK2-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 |
| // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 |
| // CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double |
| // CHECK2-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 |
| // CHECK2-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float |
| // CHECK2-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 |
| // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 |
| // CHECK2-NEXT: store double* [[G3]], double** [[TMP23]], align 8 |
| // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 8 |
| // CHECK2-NEXT: store double* [[TMP25]], double** [[TMP24]], align 8 |
| // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 |
| // CHECK2-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 8 |
| // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 |
| // CHECK2-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 8 |
| // CHECK2-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 8 dereferenceable(32) [[REF_TMP]]) |
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK2: omp.body.continue: |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK2: omp.inner.for.inc: |
| // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 |
| // CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK2: omp.inner.for.end: |
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK2: omp.loop.exit: |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK2-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@main |
| // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G1:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK3-NEXT: store double* [[G]], double** [[G1]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store double* [[G]], double** [[TMP0]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 |
| // CHECK3-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 |
| // CHECK3-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) |
| // CHECK3-NEXT: ret i32 0 |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK3-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[G2:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G13:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[_TMP4:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4 |
| // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float* |
| // CHECK3-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load double, double* [[TMP0]], align 8 |
| // CHECK3-NEXT: store double [[TMP2]], double* [[G2]], align 8 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load volatile double, double* [[TMP3]], align 4 |
| // CHECK3-NEXT: store double [[TMP4]], double* [[G13]], align 8 |
| // CHECK3-NEXT: store double* [[G13]], double** [[_TMP4]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load double*, double** [[_TMP4]], align 4 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, double*, i32*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[G2]], double* [[TMP5]], i32* [[SVAR_ADDR]], float* [[CONV]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK3-NEXT: [[SFVAR_ADDR:%.*]] = alloca float*, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[_TMP1:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK3-NEXT: [[_TMP5:%.*]] = alloca double*, align 4 |
| // CHECK3-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK3-NEXT: store double* [[G]], double** [[G_ADDR]], align 4 |
| // CHECK3-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store float* [[SFVAR]], float** [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load float*, float** [[SFVAR_ADDR]], align 4 |
| // CHECK3-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 4 |
| // CHECK3-NEXT: store double* [[TMP4]], double** [[_TMP1]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load volatile double, double* [[TMP0]], align 8 |
| // CHECK3-NEXT: store double [[TMP5]], double* [[G3]], align 8 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[_TMP1]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load volatile double, double* [[TMP6]], align 4 |
| // CHECK3-NEXT: store double [[TMP7]], double* [[G14]], align 8 |
| // CHECK3-NEXT: store double* [[G14]], double** [[_TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP2]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP8]], i32* [[SVAR6]], align 4 |
| // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[TMP3]], align 4 |
| // CHECK3-NEXT: store float [[TMP9]], float* [[SFVAR7]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 |
| // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] |
| // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 |
| // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 |
| // CHECK3-NEXT: store double [[ADD9]], double* [[G3]], align 8 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 |
| // CHECK3-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 |
| // CHECK3-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 |
| // CHECK3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 |
| // CHECK3-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double |
| // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 |
| // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float |
| // CHECK3-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 |
| // CHECK3-NEXT: store double* [[G3]], double** [[TMP23]], align 4 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4 |
| // CHECK3-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 |
| // CHECK3-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 |
| // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 |
| // CHECK3-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 |
| // CHECK3-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 |
| // CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK3-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@main |
| // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK4-NEXT: [[G1:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK4-NEXT: store double* [[G]], double** [[G1]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 0 |
| // CHECK4-NEXT: store double* [[G]], double** [[TMP0]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[CLASS_ANON]], %class.anon* [[REF_TMP]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load double*, double** [[G1]], align 4 |
| // CHECK4-NEXT: store double* [[TMP2]], double** [[TMP1]], align 4 |
| // CHECK4-NEXT: call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 4 dereferenceable(8) [[REF_TMP]]) |
| // CHECK4-NEXT: ret i32 0 |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l68 |
| // CHECK4-SAME: (double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32 [[SVAR:%.*]], i32 [[SFVAR:%.*]]) #[[ATTR2:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SFVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[G2:%.*]] = alloca double, align 8 |
| // CHECK4-NEXT: [[G13:%.*]] = alloca double, align 8 |
| // CHECK4-NEXT: [[_TMP4:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: store double* [[G]], double** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[SFVAR]], i32* [[SFVAR_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[SFVAR_ADDR]] to float* |
| // CHECK4-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load double, double* [[TMP0]], align 8 |
| // CHECK4-NEXT: store double [[TMP2]], double* [[G2]], align 8 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load double*, double** [[TMP]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load volatile double, double* [[TMP3]], align 4 |
| // CHECK4-NEXT: store double [[TMP4]], double* [[G13]], align 8 |
| // CHECK4-NEXT: store double* [[G13]], double** [[_TMP4]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load double*, double** [[_TMP4]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, double*, double*, i32*, float*)* @.omp_outlined. to void (i32*, i32*, ...)*), double* [[G2]], double* [[TMP5]], i32* [[SVAR_ADDR]], float* [[CONV]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], double* nonnull align 4 dereferenceable(8) [[G:%.*]], double* nonnull align 4 dereferenceable(8) [[G1:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]], float* nonnull align 4 dereferenceable(4) [[SFVAR:%.*]]) #[[ATTR2]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[G1_ADDR:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[SFVAR_ADDR:%.*]] = alloca float*, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[_TMP1:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[G3:%.*]] = alloca double, align 8 |
| // CHECK4-NEXT: [[G14:%.*]] = alloca double, align 8 |
| // CHECK4-NEXT: [[_TMP5:%.*]] = alloca double*, align 4 |
| // CHECK4-NEXT: [[SVAR6:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[SFVAR7:%.*]] = alloca float, align 4 |
| // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store double* [[G]], double** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store double* [[G1]], double** [[G1_ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 |
| // CHECK4-NEXT: store float* [[SFVAR]], float** [[SFVAR_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load double*, double** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load double*, double** [[G1_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load float*, float** [[SFVAR_ADDR]], align 4 |
| // CHECK4-NEXT: store double* [[TMP1]], double** [[TMP]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load double*, double** [[TMP]], align 4 |
| // CHECK4-NEXT: store double* [[TMP4]], double** [[_TMP1]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load volatile double, double* [[TMP0]], align 8 |
| // CHECK4-NEXT: store double [[TMP5]], double* [[G3]], align 8 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[_TMP1]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load volatile double, double* [[TMP6]], align 4 |
| // CHECK4-NEXT: store double [[TMP7]], double* [[G14]], align 8 |
| // CHECK4-NEXT: store double* [[G14]], double** [[_TMP5]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP2]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP8]], i32* [[SVAR6]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[TMP3]], align 4 |
| // CHECK4-NEXT: store float [[TMP9]], float* [[SFVAR7]], align 4 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 1 |
| // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK4: cond.true: |
| // CHECK4-NEXT: br label [[COND_END:%.*]] |
| // CHECK4: cond.false: |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: br label [[COND_END]] |
| // CHECK4: cond.end: |
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] |
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK4: omp.inner.for.cond: |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[CMP8:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]] |
| // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK4: omp.inner.for.body: |
| // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP17]], 1 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK4-NEXT: [[TMP18:%.*]] = load double, double* [[G3]], align 8 |
| // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[TMP18]], 1.000000e+00 |
| // CHECK4-NEXT: store double [[ADD9]], double* [[G3]], align 8 |
| // CHECK4-NEXT: [[TMP19:%.*]] = load double*, double** [[_TMP5]], align 4 |
| // CHECK4-NEXT: [[TMP20:%.*]] = load volatile double, double* [[TMP19]], align 4 |
| // CHECK4-NEXT: [[ADD10:%.*]] = fadd double [[TMP20]], 1.000000e+00 |
| // CHECK4-NEXT: store volatile double [[ADD10]], double* [[TMP19]], align 4 |
| // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[SVAR6]], align 4 |
| // CHECK4-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], 3 |
| // CHECK4-NEXT: store i32 [[ADD11]], i32* [[SVAR6]], align 4 |
| // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[SFVAR7]], align 4 |
| // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP22]] to double |
| // CHECK4-NEXT: [[ADD12:%.*]] = fadd double [[CONV]], 4.000000e+00 |
| // CHECK4-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float |
| // CHECK4-NEXT: store float [[CONV13]], float* [[SFVAR7]], align 4 |
| // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 0 |
| // CHECK4-NEXT: store double* [[G3]], double** [[TMP23]], align 4 |
| // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP25:%.*]] = load double*, double** [[_TMP5]], align 4 |
| // CHECK4-NEXT: store double* [[TMP25]], double** [[TMP24]], align 4 |
| // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 2 |
| // CHECK4-NEXT: store i32* [[SVAR6]], i32** [[TMP26]], align 4 |
| // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], %class.anon.0* [[REF_TMP]], i32 0, i32 3 |
| // CHECK4-NEXT: store float* [[SFVAR7]], float** [[TMP27]], align 4 |
| // CHECK4-NEXT: call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 4 dereferenceable(16) [[REF_TMP]]) |
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK4: omp.body.continue: |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK4: omp.inner.for.inc: |
| // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], 1 |
| // CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK4: omp.inner.for.end: |
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK4: omp.loop.exit: |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK4-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@main |
| // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK9-NEXT: [[G1:%.*]] = alloca double*, align 8 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK9-NEXT: store double* [[G]], double** [[G1]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK9-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 |
| // CHECK9-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 |
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 |
| // CHECK9-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP13]], align 8 |
| // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 |
| // CHECK9-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP18]], align 8 |
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** |
| // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 |
| // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** |
| // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 |
| // CHECK9-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP23]], align 8 |
| // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** |
| // CHECK9-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 |
| // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** |
| // CHECK9-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 |
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP28]], align 8 |
| // CHECK9-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK9-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 |
| // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK9-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 |
| // CHECK9-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP33]], align 8 |
| // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) |
| // CHECK9-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK9-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 |
| // CHECK9-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK9: omp_offload.failed: |
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] |
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK9: omp_offload.cont: |
| // CHECK9-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() |
| // CHECK9-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done3: |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP39]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 |
| // CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* |
| // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* |
| // CHECK9-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK9-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 |
| // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* |
| // CHECK9-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK9-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done6: |
| // CHECK9-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 |
| // CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* |
| // CHECK9-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) |
| // CHECK9-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 |
| // CHECK9-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 |
| // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK9: cond.true: |
| // CHECK9-NEXT: br label [[COND_END:%.*]] |
| // CHECK9: cond.false: |
| // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: br label [[COND_END]] |
| // CHECK9: cond.end: |
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] |
| // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK9: omp.inner.for.cond: |
| // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] |
| // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK9: omp.inner.for.cond.cleanup: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK9: omp.inner.for.body: |
| // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK9-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK9-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 |
| // CHECK9-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] |
| // CHECK9-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* |
| // CHECK9-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) |
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK9: omp.body.continue: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK9: omp.inner.for.inc: |
| // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 |
| // CHECK9-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK9: omp.inner.for.end: |
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK9: omp.loop.exit: |
| // CHECK9-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done15: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK9-SAME: () #[[ATTR5:[0-9]+]] comdat { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK9-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK9-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK9-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK9-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK9-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) |
| // CHECK9-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK9-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) |
| // CHECK9-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* |
| // CHECK9-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK9-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 |
| // CHECK9-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP11]], align 8 |
| // CHECK9-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 |
| // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK9-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP16]], align 8 |
| // CHECK9-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** |
| // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 |
| // CHECK9-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK9-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** |
| // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 |
| // CHECK9-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP21]], align 8 |
| // CHECK9-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** |
| // CHECK9-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 |
| // CHECK9-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK9-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** |
| // CHECK9-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 |
| // CHECK9-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK9-NEXT: store i8* null, i8** [[TMP26]], align 8 |
| // CHECK9-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK9-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) |
| // CHECK9-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK9-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 |
| // CHECK9-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK9: omp_offload.failed: |
| // CHECK9-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] |
| // CHECK9-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK9: omp_offload.cont: |
| // CHECK9-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done2: |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK9-NEXT: ret i32 [[TMP32]] |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store float 0.000000e+00, float* [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: store float [[TMP0]], float* [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK9-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK9-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK9-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* |
| // CHECK9-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK9-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK9-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 |
| // CHECK9-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK9-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK9-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK9-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK9-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 |
| // CHECK9-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK9-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) |
| // CHECK9-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* |
| // CHECK9-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK9: omp.arraycpy.body: |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK9-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK9-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK9-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] |
| // CHECK9-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK9: omp.arraycpy.done6: |
| // CHECK9-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 |
| // CHECK9-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* |
| // CHECK9-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) |
| // CHECK9-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 |
| // CHECK9-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK9: cond.true: |
| // CHECK9-NEXT: br label [[COND_END:%.*]] |
| // CHECK9: cond.false: |
| // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: br label [[COND_END]] |
| // CHECK9: cond.end: |
| // CHECK9-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] |
| // CHECK9-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK9: omp.inner.for.cond: |
| // CHECK9-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK9-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] |
| // CHECK9-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK9: omp.inner.for.cond.cleanup: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK9: omp.inner.for.body: |
| // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 |
| // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK9-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK9-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 |
| // CHECK9-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 |
| // CHECK9-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 |
| // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] |
| // CHECK9-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* |
| // CHECK9-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* |
| // CHECK9-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) |
| // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK9: omp.body.continue: |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK9: omp.inner.for.inc: |
| // CHECK9-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 |
| // CHECK9-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK9: omp.inner.for.end: |
| // CHECK9-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK9: omp.loop.exit: |
| // CHECK9-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK9-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 |
| // CHECK9-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 |
| // CHECK9-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK9: arraydestroy.body: |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK9-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK9-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK9-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK9-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK9: arraydestroy.done14: |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: store i32 0, i32* [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK9-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK9-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK9-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK9-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK9-SAME: () #[[ATTR6:[0-9]+]] { |
| // CHECK9-NEXT: entry: |
| // CHECK9-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK9-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@main |
| // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK10-NEXT: [[G1:%.*]] = alloca double*, align 8 |
| // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[SVAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 |
| // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK10-NEXT: store double* [[G]], double** [[G1]], align 8 |
| // CHECK10-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i64 8, i1 false) |
| // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 |
| // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK10-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK10-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 8 |
| // CHECK10-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP5]], i32* [[CONV1]], align 4 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[SVAR_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 |
| // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 |
| // CHECK10-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP13]], align 8 |
| // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 |
| // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK10-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 8 |
| // CHECK10-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP18]], align 8 |
| // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** |
| // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 8 |
| // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK10-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** |
| // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 8 |
| // CHECK10-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP23]], align 8 |
| // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** |
| // CHECK10-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 8 |
| // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK10-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** |
| // CHECK10-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 8 |
| // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP28]], align 8 |
| // CHECK10-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK10-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP30]], align 8 |
| // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK10-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP6]], i64* [[TMP32]], align 8 |
| // CHECK10-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP33]], align 8 |
| // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) |
| // CHECK10-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK10-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 |
| // CHECK10-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK10: omp_offload.failed: |
| // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i64 [[TMP6]]) #[[ATTR4:[0-9]+]] |
| // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK10: omp_offload.cont: |
| // CHECK10-NEXT: [[CALL:%.*]] = call signext i32 @_Z5tmainIiET_v() |
| // CHECK10-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 |
| // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 |
| // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK10: arraydestroy.body: |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE3:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK10: arraydestroy.done3: |
| // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK10-NEXT: ret i32 [[TMP39]] |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 |
| // CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i64 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 |
| // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[SVAR]], i64* [[SVAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[SVAR_ADDR]] to i32* |
| // CHECK10-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[CONV1]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8 |
| // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 8 |
| // CHECK10-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 8 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 |
| // CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i64 8, i1 false) |
| // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* |
| // CHECK10-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i64 2 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] |
| // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK10: omp.arraycpy.body: |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK10-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i64 4, i1 false) |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] |
| // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK10: omp.arraycpy.done6: |
| // CHECK10-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 8 |
| // CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* |
| // CHECK10-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i64 4, i1 false) |
| // CHECK10-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 8 |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 |
| // CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 |
| // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] |
| // CHECK10-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK10: omp.inner.for.cond.cleanup: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP26]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK10-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 |
| // CHECK10-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 8 |
| // CHECK10-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP28]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i64 0, i64 [[IDXPROM11]] |
| // CHECK10-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX12]] to i8* |
| // CHECK10-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i64 4, i1 false) |
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK10: omp.body.continue: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP31]], 1 |
| // CHECK10-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) |
| // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAY_BEGIN14:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN14]], i64 2 |
| // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK10: arraydestroy.body: |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK10-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN14]] |
| // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK10: arraydestroy.done15: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK10-SAME: () #[[ATTR5:[0-9]+]] comdat { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK10-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK10-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK10-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[T_VAR_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK10-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK10-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK10-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK10-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i64 8, i1 false) |
| // CHECK10-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 |
| // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 signext 1) |
| // CHECK10-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1 |
| // CHECK10-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 signext 2) |
| // CHECK10-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[T_VAR_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP8]], align 8 |
| // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK10-NEXT: store i64 [[TMP3]], i64* [[TMP10]], align 8 |
| // CHECK10-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP11]], align 8 |
| // CHECK10-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK10-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 8 |
| // CHECK10-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK10-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 8 |
| // CHECK10-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP16]], align 8 |
| // CHECK10-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK10-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** |
| // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 8 |
| // CHECK10-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK10-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** |
| // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 8 |
| // CHECK10-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP21]], align 8 |
| // CHECK10-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK10-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** |
| // CHECK10-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 8 |
| // CHECK10-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK10-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** |
| // CHECK10-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 8 |
| // CHECK10-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK10-NEXT: store i8* null, i8** [[TMP26]], align 8 |
| // CHECK10-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK10-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) |
| // CHECK10-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK10-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 |
| // CHECK10-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK10: omp_offload.failed: |
| // CHECK10-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i64 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] |
| // CHECK10-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK10: omp_offload.cont: |
| // CHECK10-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 |
| // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK10: arraydestroy.body: |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK10: arraydestroy.done2: |
| // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK10-NEXT: ret i32 [[TMP32]] |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK10-NEXT: store float 0.000000e+00, float* [[F]], align 4 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: store float [[TMP0]], float* [[F]], align 4 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK10-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8 |
| // CHECK10-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 signext [[TMP0]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK10-SAME: (i64 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 |
| // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: store i64 [[T_VAR]], i64* [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[T_VAR_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[CONV]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8 |
| // CHECK10-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8 |
| // CHECK10-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK10-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK10-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK10-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 8 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 |
| // CHECK10-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK10-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 8, i1 false) |
| // CHECK10-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* |
| // CHECK10-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i64 2 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] |
| // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK10: omp.arraycpy.body: |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK10-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK10-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i64 4, i1 false) |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK10-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] |
| // CHECK10-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK10: omp.arraycpy.done6: |
| // CHECK10-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 8 |
| // CHECK10-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* |
| // CHECK10-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i64 4, i1 false) |
| // CHECK10-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 8 |
| // CHECK10-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 |
| // CHECK10-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] |
| // CHECK10-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK10: omp.inner.for.cond.cleanup: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP24]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i64 0, i64 [[IDXPROM]] |
| // CHECK10-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 |
| // CHECK10-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 8 |
| // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP26]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i64 0, i64 [[IDXPROM10]] |
| // CHECK10-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX11]] to i8* |
| // CHECK10-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* |
| // CHECK10-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i64 4, i1 false) |
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK10: omp.body.continue: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP29]], 1 |
| // CHECK10-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) |
| // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN13]], i64 2 |
| // CHECK10-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK10: arraydestroy.body: |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK10-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1 |
| // CHECK10-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK10-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK10-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK10: arraydestroy.done14: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK10-NEXT: store i32 0, i32* [[F]], align 4 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 signext [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK10-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8 |
| // CHECK10-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8 |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK10-SAME: () #[[ATTR6:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@main |
| // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK11-NEXT: [[G1:%.*]] = alloca double*, align 4 |
| // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK11-NEXT: store double* [[G]], double** [[G1]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK11-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK11-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 |
| // CHECK11-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP13]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP18]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** |
| // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** |
| // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP23]], align 4 |
| // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** |
| // CHECK11-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** |
| // CHECK11-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 |
| // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP28]], align 4 |
| // CHECK11-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK11-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 |
| // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK11-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 |
| // CHECK11-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP33]], align 4 |
| // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) |
| // CHECK11-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK11-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 |
| // CHECK11-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK11: omp_offload.failed: |
| // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] |
| // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK11: omp_offload.cont: |
| // CHECK11-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() |
| // CHECK11-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done2: |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK11-NEXT: ret i32 [[TMP39]] |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 |
| // CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK11-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* |
| // CHECK11-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK11: omp.arraycpy.body: |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK11-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK11: omp.arraycpy.done6: |
| // CHECK11-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* |
| // CHECK11-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) |
| // CHECK11-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 |
| // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] |
| // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK11: omp.inner.for.cond.cleanup: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] |
| // CHECK11-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 |
| // CHECK11-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] |
| // CHECK11-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* |
| // CHECK11-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 |
| // CHECK11-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done14: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK11-SAME: () #[[ATTR5:[0-9]+]] comdat { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK11-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK11-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK11-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK11-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) |
| // CHECK11-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK11-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) |
| // CHECK11-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP11]], align 4 |
| // CHECK11-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 |
| // CHECK11-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK11-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP16]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** |
| // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK11-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** |
| // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP21]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** |
| // CHECK11-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 |
| // CHECK11-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK11-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** |
| // CHECK11-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK11-NEXT: store i8* null, i8** [[TMP26]], align 4 |
| // CHECK11-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK11-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) |
| // CHECK11-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK11-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 |
| // CHECK11-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK11: omp_offload.failed: |
| // CHECK11-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] |
| // CHECK11-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK11: omp_offload.cont: |
| // CHECK11-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done2: |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK11-NEXT: ret i32 [[TMP32]] |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store float 0.000000e+00, float* [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store float [[TMP0]], float* [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK11-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK11-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK11-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK11-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 |
| // CHECK11-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK11-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK11-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK11-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK11-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 |
| // CHECK11-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK11-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) |
| // CHECK11-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* |
| // CHECK11-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK11: omp.arraycpy.body: |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK11-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK11-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK11-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] |
| // CHECK11-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK11: omp.arraycpy.done6: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* |
| // CHECK11-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) |
| // CHECK11-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 |
| // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] |
| // CHECK11-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK11: omp.inner.for.cond.cleanup: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] |
| // CHECK11-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 |
| // CHECK11-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 |
| // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] |
| // CHECK11-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* |
| // CHECK11-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* |
| // CHECK11-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 |
| // CHECK11-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK11-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 |
| // CHECK11-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK11: arraydestroy.body: |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK11-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK11-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK11-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] |
| // CHECK11-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK11: arraydestroy.done13: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: store i32 0, i32* [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK11-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK11-SAME: () #[[ATTR6:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@main |
| // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[G:%.*]] = alloca double, align 8 |
| // CHECK12-NEXT: [[G1:%.*]] = alloca double*, align 4 |
| // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[SVAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK12-NEXT: store double* [[G]], double** [[G1]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const.main.vec to i8*), i32 8, i1 false) |
| // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00) |
| // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK12-NEXT: call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00) |
| // CHECK12-NEXT: store %struct.S* [[TEST]], %struct.S** [[VAR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S*, %struct.S** [[VAR]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[TMP1]], %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* @_ZZ4mainE4svar, align 4 |
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[SVAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[SVAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 |
| // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP13]], align 4 |
| // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK12-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [2 x i32]** |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP17]], align 4 |
| // CHECK12-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP18]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S]** |
| // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP20]], align 4 |
| // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to [2 x %struct.S]** |
| // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[TMP22]], align 4 |
| // CHECK12-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP23]], align 4 |
| // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S** |
| // CHECK12-NEXT: store %struct.S* [[TMP7]], %struct.S** [[TMP25]], align 4 |
| // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S** |
| // CHECK12-NEXT: store %struct.S* [[TMP8]], %struct.S** [[TMP27]], align 4 |
| // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP28]], align 4 |
| // CHECK12-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 |
| // CHECK12-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP30]], align 4 |
| // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 |
| // CHECK12-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP6]], i32* [[TMP32]], align 4 |
| // CHECK12-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP33]], align 4 |
| // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2:[0-9]+]], i64 -1, i64 2) |
| // CHECK12-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103.region_id, i32 5, i8** [[TMP34]], i8** [[TMP35]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK12-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 |
| // CHECK12-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK12: omp_offload.failed: |
| // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S]* [[S_ARR]], %struct.S* [[TMP4]], i32 [[TMP6]]) #[[ATTR4:[0-9]+]] |
| // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK12: omp_offload.cont: |
| // CHECK12-NEXT: [[CALL:%.*]] = call i32 @_Z5tmainIiET_v() |
| // CHECK12-NEXT: store i32 [[CALL]], i32* [[RETVAL]], align 4 |
| // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 |
| // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK12: arraydestroy.body: |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP38]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK12: arraydestroy.done2: |
| // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[TMP39:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK12-NEXT: ret i32 [[TMP39]] |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l103 |
| // CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32 [[SVAR:%.*]]) #[[ATTR3:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 |
| // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[SVAR]], i32* [[SVAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[TMP2]], %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S]* [[TMP1]], %struct.S* [[TMP3]], i32* [[SVAR_ADDR]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]], i32* nonnull align 4 dereferenceable(4) [[SVAR:%.*]]) #[[ATTR3]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 4 |
| // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[SVAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S], align 4 |
| // CHECK12-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S:%.*]], align 4 |
| // CHECK12-NEXT: [[_TMP8:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[SVAR9:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[SVAR]], i32** [[SVAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[SVAR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[TMP3]], %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S*, %struct.S** [[TMP]], align 4 |
| // CHECK12-NEXT: store %struct.S* [[TMP5]], %struct.S** [[_TMP1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP6]], i32* [[T_VAR3]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP7]], i8* align 4 [[TMP8]], i32 8, i1 false) |
| // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP9:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S* |
| // CHECK12-NEXT: [[TMP10:%.*]] = getelementptr [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN]], i32 2 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP10]] |
| // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK12: omp.arraycpy.body: |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP9]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK12-NEXT: [[TMP12:%.*]] = bitcast %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP11]], i8* align 4 [[TMP12]], i32 4, i1 false) |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP10]] |
| // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK12: omp.arraycpy.done6: |
| // CHECK12-NEXT: [[TMP13:%.*]] = load %struct.S*, %struct.S** [[_TMP1]], align 4 |
| // CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S* [[VAR7]] to i8* |
| // CHECK12-NEXT: [[TMP15:%.*]] = bitcast %struct.S* [[TMP13]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP14]], i8* align 4 [[TMP15]], i32 4, i1 false) |
| // CHECK12-NEXT: store %struct.S* [[VAR7]], %struct.S** [[_TMP8]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP4]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP16]], i32* [[SVAR9]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP18]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP19]], 1 |
| // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP20]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP21]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP22]], [[TMP23]] |
| // CHECK12-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK12: omp.inner.for.cond.cleanup: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP24]], 1 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP26]] |
| // CHECK12-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX]], align 4 |
| // CHECK12-NEXT: [[TMP27:%.*]] = load %struct.S*, %struct.S** [[_TMP8]], align 4 |
| // CHECK12-NEXT: [[TMP28:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 [[TMP28]] |
| // CHECK12-NEXT: [[TMP29:%.*]] = bitcast %struct.S* [[ARRAYIDX11]] to i8* |
| // CHECK12-NEXT: [[TMP30:%.*]] = bitcast %struct.S* [[TMP27]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP29]], i8* align 4 [[TMP30]], i32 4, i1 false) |
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK12: omp.body.continue: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP31]], 1 |
| // CHECK12-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP32]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP33]]) |
| // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAY_BEGIN13:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAY_BEGIN13]], i32 2 |
| // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK12: arraydestroy.body: |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP34]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK12-NEXT: call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN13]] |
| // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE14:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK12: arraydestroy.done14: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v |
| // CHECK12-SAME: () #[[ATTR5:[0-9]+]] comdat { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK12-NEXT: [[T_VAR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC:%.*]] = alloca [2 x i32], align 4 |
| // CHECK12-NEXT: [[S_ARR:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK12-NEXT: [[VAR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[T_VAR_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK12-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) |
| // CHECK12-NEXT: store i32 0, i32* [[T_VAR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [2 x i32]* [[VEC]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP0]], i8* align 4 bitcast ([2 x i32]* @__const._Z5tmainIiET_v.vec to i8*), i32 8, i1 false) |
| // CHECK12-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1) |
| // CHECK12-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYINIT_BEGIN]], i32 1 |
| // CHECK12-NEXT: call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2) |
| // CHECK12-NEXT: store %struct.S.0* [[TEST]], %struct.S.0** [[VAR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[TMP1]], %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP2]], i32* [[T_VAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[T_VAR_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP8]], align 4 |
| // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK12-NEXT: store i32 [[TMP3]], i32* [[TMP10]], align 4 |
| // CHECK12-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP11]], align 4 |
| // CHECK12-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK12-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to [2 x i32]** |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP13]], align 4 |
| // CHECK12-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK12-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [2 x i32]** |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[TMP15]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP16]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [2 x %struct.S.0]** |
| // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP18]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK12-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to [2 x %struct.S.0]** |
| // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[TMP20]], align 4 |
| // CHECK12-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP21]], align 4 |
| // CHECK12-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to %struct.S.0** |
| // CHECK12-NEXT: store %struct.S.0* [[TMP5]], %struct.S.0** [[TMP23]], align 4 |
| // CHECK12-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK12-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to %struct.S.0** |
| // CHECK12-NEXT: store %struct.S.0* [[TMP6]], %struct.S.0** [[TMP25]], align 4 |
| // CHECK12-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK12-NEXT: store i8* null, i8** [[TMP26]], align 4 |
| // CHECK12-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK12-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i64 2) |
| // CHECK12-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK12-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 |
| // CHECK12-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK12: omp_offload.failed: |
| // CHECK12-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49(i32 [[TMP3]], [2 x i32]* [[VEC]], [2 x %struct.S.0]* [[S_ARR]], %struct.S.0* [[TMP4]]) #[[ATTR4]] |
| // CHECK12-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK12: omp_offload.cont: |
| // CHECK12-NEXT: store i32 0, i32* [[RETVAL]], align 4 |
| // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 |
| // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK12: arraydestroy.body: |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP31]], [[OMP_OFFLOAD_CONT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]] |
| // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE2:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK12: arraydestroy.done2: |
| // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[TMP32:%.*]] = load i32, i32* [[RETVAL]], align 4 |
| // CHECK12-NEXT: ret i32 [[TMP32]] |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: store float 0.000000e+00, float* [[F]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca float, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store float [[A]], float* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store float [[TMP0]], float* [[F]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev |
| // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S*, align 4 |
| // CHECK12-NEXT: store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z5tmainIiET_v_l49 |
| // CHECK12-SAME: (i32 [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 |
| // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: store i32 [[T_VAR]], i32* [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[TMP2]], %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[T_VAR_ADDR]], [2 x i32]* [[TMP0]], [2 x %struct.S.0]* [[TMP1]], %struct.S.0* [[TMP3]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR3]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[T_VAR_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 4 |
| // CHECK12-NEXT: [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 4 |
| // CHECK12-NEXT: [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[_TMP1:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[_TMP2:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[T_VAR3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[VEC4:%.*]] = alloca [2 x i32], align 4 |
| // CHECK12-NEXT: [[S_ARR5:%.*]] = alloca [2 x %struct.S.0], align 4 |
| // CHECK12-NEXT: [[VAR7:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4 |
| // CHECK12-NEXT: [[_TMP8:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[TMP3]], %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load %struct.S.0*, %struct.S.0** [[TMP]], align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[TMP4]], %struct.S.0** [[_TMP1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[T_VAR3]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = bitcast [2 x i32]* [[VEC4]] to i8* |
| // CHECK12-NEXT: [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i32 8, i1 false) |
| // CHECK12-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0* |
| // CHECK12-NEXT: [[TMP9:%.*]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN]], i32 2 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP9]] |
| // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE6:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]] |
| // CHECK12: omp.arraycpy.body: |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[ENTRY:%.*]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[ENTRY]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ] |
| // CHECK12-NEXT: [[TMP10:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]] to i8* |
| // CHECK12-NEXT: [[TMP11:%.*]] = bitcast %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 [[TMP11]], i32 4, i1 false) |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1 |
| // CHECK12-NEXT: [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]] |
| // CHECK12-NEXT: br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE6]], label [[OMP_ARRAYCPY_BODY]] |
| // CHECK12: omp.arraycpy.done6: |
| // CHECK12-NEXT: [[TMP12:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP1]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = bitcast %struct.S.0* [[VAR7]] to i8* |
| // CHECK12-NEXT: [[TMP14:%.*]] = bitcast %struct.S.0* [[TMP12]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 [[TMP14]], i32 4, i1 false) |
| // CHECK12-NEXT: store %struct.S.0* [[VAR7]], %struct.S.0** [[_TMP8]], align 4 |
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[TMP15]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP16]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP17]], 1 |
| // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 1, [[COND_TRUE]] ], [ [[TMP18]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP19]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP9:%.*]] = icmp sle i32 [[TMP20]], [[TMP21]] |
| // CHECK12-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] |
| // CHECK12: omp.inner.for.cond.cleanup: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP22]], 1 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP23:%.*]] = load i32, i32* [[T_VAR3]], align 4 |
| // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC4]], i32 0, i32 [[TMP24]] |
| // CHECK12-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX]], align 4 |
| // CHECK12-NEXT: [[TMP25:%.*]] = load %struct.S.0*, %struct.S.0** [[_TMP8]], align 4 |
| // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 [[TMP26]] |
| // CHECK12-NEXT: [[TMP27:%.*]] = bitcast %struct.S.0* [[ARRAYIDX10]] to i8* |
| // CHECK12-NEXT: [[TMP28:%.*]] = bitcast %struct.S.0* [[TMP25]] to i8* |
| // CHECK12-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP27]], i8* align 4 [[TMP28]], i32 4, i1 false) |
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK12: omp.body.continue: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP29]], 1 |
| // CHECK12-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP30]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP31]]) |
| // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[VAR7]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAY_BEGIN12:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR5]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAY_BEGIN12]], i32 2 |
| // CHECK12-NEXT: br label [[ARRAYDESTROY_BODY:%.*]] |
| // CHECK12: arraydestroy.body: |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP32]], [[OMP_LOOP_EXIT]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ] |
| // CHECK12-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i32 -1 |
| // CHECK12-NEXT: call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]] |
| // CHECK12-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN12]] |
| // CHECK12-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE13:%.*]], label [[ARRAYDESTROY_BODY]] |
| // CHECK12: arraydestroy.done13: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]] |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: store i32 0, i32* [[F]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP0]], i32* [[F]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev |
| // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 4 |
| // CHECK12-NEXT: store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 4 |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK12-SAME: () #[[ATTR6:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK12-NEXT: ret void |
| // |
| // |
