)]}'
{
  "commit": "76d98cfcc40e9a351efc52287338f0fd5d4402fb",
  "tree": "8e6831347892b8a4bc9b9e26490fd47ffa945a5c",
  "parents": [
    "155359c1f2bda7fb8d4e8001157ecea03689df68"
  ],
  "author": {
    "name": "Mel Chen",
    "email": "mel.chen@sifive.com",
    "time": "Tue Aug 05 16:08:13 2025 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Aug 05 16:08:13 2025 +0800"
  },
  "message": "[RISCV][TTI] Enable masked interleave access  (#151665)\n\nNow that support for masked loads/stores of interleave groups has\nlanded, we can enable the loop vectorizer to generate masked interleave\naccess where applicable.\n\nThis improves vectorization in several ways:\n* Internal predication support: This enables interleave group\nvectorization for loops with internal control flow predication, provided\nall members of the group share the same predicate. Gaps in interleave\ngroups are still not efficiently handled by masking, so masking for gaps\nremains disabled for now.\n* Tail folding: This allows tail folding of loops with interleave groups\nby using masking. Without this, vectorized loops with interleaves would\nfall back to using separate gather/scatter accesses, which can be\nsignificantly less efficient.\n\n\"[RISCV][TTI] Enable masked interleave access for scalable vector\n(#149981)\" was reverted by 5294793bdcf6ca142f7a0df897638bd4e85ed1a7 due\nto triggering an assertion. The issue has been addressed in the patch\n\"[LV] Fix gap mask requirement for interleaved access (#151105)\". On the\nother hand, this patch also enable fixed-length masked interleave access\n(#150624) since support for fixed-length has also been landed\n992118cb4deab139ae384bb85f03225a9a21b008.\n\n---------\n\nCo-authored-by: Philip Reames \u003cpreames@rivosinc.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0d5eb86bf899c6a593883254a6e85817f302ccf7",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp",
      "new_id": "67f924aadc8c0fda8852cfb3a42bf87be925b1e1",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp"
    },
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      "old_id": "d62d99cf31899549a9ed0036d37e2fcfc832f7c6",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h",
      "new_id": "05d504cbcb6bb5413929c3f6e31f5dd44030aa62",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h"
    },
    {
      "type": "modify",
      "old_id": "6f20376e08d859b32432dd4190603a3b2ef6d93f",
      "old_mode": 33188,
      "old_path": "llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll",
      "new_id": "976ce77d2ba290f0dae0106959ed6b56a6f1c32b",
      "new_mode": 33188,
      "new_path": "llvm/test/Transforms/LoopVectorize/RISCV/interleaved-masked-access.ll"
    },
    {
      "type": "modify",
      "old_id": "1f7c51800f3e0aa33b9121a9435ad04710c8f801",
      "old_mode": 33188,
      "old_path": "llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll",
      "new_id": "8d987a94d383d1ef293d207cf0cae99b9df94635",
      "new_mode": 33188,
      "new_path": "llvm/test/Transforms/LoopVectorize/RISCV/tail-folding-interleave.ll"
    }
  ]
}