| { |
| "arrays": [ |
| { |
| "name": "MemRef_arg", |
| "sizes": [ |
| "*" |
| ], |
| "type": "i32" |
| }, |
| { |
| "name": "MemRef_arg2", |
| "sizes": [ |
| "*" |
| ], |
| "type": "i32" |
| } |
| ], |
| "context": "[arg1] -> { : -9223372036854775808 <= arg1 <= 9223372036854775807 }", |
| "name": "%bb3---%bb19", |
| "statements": [ |
| { |
| "accesses": [ |
| { |
| "kind": "read", |
| "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg[1 + i0] }" |
| }, |
| { |
| "kind": "write", |
| "relation": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> MemRef_arg2[1 + i0] : arg1 <= 2305843009213693952 }" |
| } |
| ], |
| "domain": "[arg1] -> { Stmt_bb3__TO__bb10[i0] : 0 <= i0 <= -2 + arg1 }", |
| "name": "Stmt_bb3__TO__bb10", |
| "schedule": "[arg1] -> { Stmt_bb3__TO__bb10[i0] -> [i0, 0] }" |
| }, |
| { |
| "accesses": [ |
| { |
| "kind": "read", |
| "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }" |
| }, |
| { |
| "kind": "write", |
| "relation": "[arg1] -> { Stmt_bb10[i0] -> MemRef_arg2[1 + i0] }" |
| } |
| ], |
| "domain": "[arg1] -> { Stmt_bb10[i0] : 0 <= i0 <= -2 + arg1 }", |
| "name": "Stmt_bb10", |
| "schedule": "[arg1] -> { Stmt_bb10[i0] -> [i0, 1] }" |
| } |
| ] |
| } |