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llvm / llvm-project / 733ad3fdebf782be5afffdb8310a0ce15675086c
commit733ad3fdebf782be5afffdb8310a0ce15675086c[log] [tgz]
authorKito Cheng <kito.cheng@sifive.com>Fri Mar 07 14:09:26 2025 +0800
committerGitHub <noreply@github.com>Fri Mar 07 14:09:26 2025 +0800
treed46669d7366337a7b14dcfffb180e2974068efd9
parentbedb9077c38cf01a3f9303d68599ea95677be5b7 [diff]
[LTO] Override TargetABI from module flags if present when creating TargetMachine (#126497)

…argetMachine

RISC-V's data layout is determined by the ABI, not just the target
triple. However, the TargetMachine is created using the data layout from
the target triple, which is not always correct. This patch uses the
target ABI from the module and passes it to the TargetMachine, ensuring
that the data layout is set correctly according to the ABI.

The same problem will happen with other targets like MIPS, but
unfortunately, MIPS didn't emit the target-abi into the module flags, so
this patch only fixes the issue for RISC-V.

NOTE: MIPS with -mabi=n32 can trigger the same issue.

Another possible solution is add new parameter to the TargetMachine
constructor, but that would require changes in all the targets.
5 files changed
tree: d46669d7366337a7b14dcfffb180e2974068efd9
  1. .ci/
  2. .github/
  3. bolt/
  4. clang/
  5. clang-tools-extra/
  6. cmake/
  7. compiler-rt/
  8. cross-project-tests/
  9. flang/
  10. flang-rt/
  11. libc/
  12. libclc/
  13. libcxx/
  14. libcxxabi/
  15. libunwind/
  16. lld/
  17. lldb/
  18. llvm/
  19. llvm-libgcc/
  20. mlir/
  21. offload/
  22. openmp/
  23. polly/
  24. pstl/
  25. runtimes/
  26. third-party/
  27. utils/
  28. .clang-format
  29. .clang-tidy
  30. .git-blame-ignore-revs
  31. .gitattributes
  32. .gitignore
  33. .mailmap
  34. CODE_OF_CONDUCT.md
  35. CONTRIBUTING.md
  36. LICENSE.TXT
  37. pyproject.toml
  38. README.md
  39. SECURITY.md
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