diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
index 74192cb..70d18ed 100644
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -541,10 +541,12 @@
           if (!P1 || !P2)
             break;
 
-          // Remove the passed FRSP instruction if it only feeds this MI and
-          // set any uses of that FRSP (in this MI) to the source of the FRSP.
+          // Remove the passed FRSP/XSRSP instruction if it only feeds this MI
+          // and set any uses of that FRSP/XSRSP (in this MI) to the source of
+          // the FRSP/XSRSP.
           auto removeFRSPIfPossible = [&](MachineInstr *RoundInstr) {
-            if (RoundInstr->getOpcode() == PPC::FRSP &&
+            unsigned Opc = RoundInstr->getOpcode();
+            if ((Opc == PPC::FRSP || Opc == PPC::XSRSP) &&
                 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
               Simplified = true;
               Register ConvReg1 = RoundInstr->getOperand(1).getReg();
@@ -554,7 +556,7 @@
                 if (Use.getOperand(i).isReg() &&
                     Use.getOperand(i).getReg() == FRSPDefines)
                   Use.getOperand(i).setReg(ConvReg1);
-              LLVM_DEBUG(dbgs() << "Removing redundant FRSP:\n");
+              LLVM_DEBUG(dbgs() << "Removing redundant FRSP/XSRSP:\n");
               LLVM_DEBUG(RoundInstr->dump());
               LLVM_DEBUG(dbgs() << "As it feeds instruction:\n");
               LLVM_DEBUG(MI.dump());
diff --git a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir
index 15c1c4e..0cfeb94 100644
--- a/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir
+++ b/llvm/test/CodeGen/PowerPC/mi-simplify-code.mir
@@ -56,7 +56,7 @@
 # CHECK-LABEL: remove_xsrsp
 # CHECK: sldi 4, 4, 2
 # CHECK-NEXT: lfsux 0, 3, 4
-# CHECK-NEXT: xsrsp 0, 0
+# CHECK-NOT: xsrsp
 # CHECK-NEXT: lfs 1, 8(3)
 # CHECK-NEXT: xxmrghd	0, 1, 0
 # CHECK-NEXT: xvcvdpsp 34, 0