)]}'
{
  "commit": "706241344808fdcb1c8ef58383c5b2599884779e",
  "tree": "f11dd680055b59194810df91a8ce7c8cc669dca4",
  "parents": [
    "47a149729108ccce763c39ac64336cbc2cfcf490"
  ],
  "author": {
    "name": "Alexey Karyakin",
    "email": "akaryaki@qti.qualcomm.com",
    "time": "Wed May 06 10:45:55 2026 -0500"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed May 06 10:45:55 2026 -0500"
  },
  "message": "[Hexagon] Correctly split masked loads/stores after widening (#190689)\n\nNon-power of 2 masked loads and stores are first widened to a power of 2\nsize. If the original vector was larger than the single HVX register\nsize, they become multiples of the double HVX register size (e.g.\nv64f32, v128f32). Since double vector types are legal but do not support\nmasked operations, they are split during custom lowering.\n\nMemoryVT is not changed during widening and the original code assumed\nthat MemoryVT is the same as the operand type and always equal to the\ndouble HVX register size.\n\nFor example, @llvm.masked.store.v80f32.p0 is first widened to v128f32,\nthen split into two v64f32 (MemoryVT \u003d v64f32 and v16f32). The first\nhalf was lowered correctly but the second one could not be split due to\nthe unexpected v16f32 MemoryVT.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0a8d2c0599d9c9742333a3cd4258320508e0bf59",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp",
      "new_id": "744140a61c22e31f4dffc8bf32ce043eb845604f",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "4b62197e1bf848266b4736025a6aa7781bfb0051",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/Hexagon/autohvx/masked-vmem-multi.ll"
    }
  ]
}