[CIR][AArch64] Upstream NEON shift left builtins (#186406)

This PR adds CIR generation for the following AArch64 NEON builtins:

__builtin_neon_vshld_n_s64 and __builtin_neon_vshld_n_u64 (constant
shifts)

extracted the constant value and use it directly for shift left

__builtin_neon_vshld_s64  and __builtin_neon_vshld_u64 (variable shifts)
there is an existing function to handles SISD (SIngle Instruction Single
Data), reusing this to create the right CIR instructions


__builtin_neon_vshld_s64 -- call i64 @llvm.aarch64.neon.sshl.i64(i64
[[A]], i64 [[B]])
__builtin_neon_vshld_u64 -- call i64 @llvm.aarch64.neon.ushl.i64(i64
[[A]], i64 [[B]])

added test cases in intrinsics.c by looking at the test cases present in

https://github.com/llvm/llvm-project/blob/main/clang/test/CodeGen/AArch64/neon-shifts.c

before adding the code it gave a not implemented error and after adding
the code changes the error is not present the code succeeds.


ran the test cases using 
```
bin/llvm-lit -v  \
  /Users/albertbolt/projects/llvm-project/clang/test/CodeGen/AArch64/neon/intrinsics.c
```

#185382

---------

Co-authored-by: Andrzej WarzyƄski <andrzej.warzynski@gmail.com>
3 files changed
tree: 4996639b667465eec9712209e5b1eb9841086bdb
  1. .ci/
  2. .github/
  3. bolt/
  4. clang/
  5. clang-tools-extra/
  6. cmake/
  7. compiler-rt/
  8. cross-project-tests/
  9. flang/
  10. flang-rt/
  11. libc/
  12. libclc/
  13. libcxx/
  14. libcxxabi/
  15. libsycl/
  16. libunwind/
  17. lld/
  18. lldb/
  19. llvm/
  20. llvm-libgcc/
  21. mlir/
  22. offload/
  23. openmp/
  24. orc-rt/
  25. polly/
  26. runtimes/
  27. third-party/
  28. utils/
  29. .clang-format
  30. .clang-format-ignore
  31. .clang-tidy
  32. .git-blame-ignore-revs
  33. .gitattributes
  34. .gitignore
  35. .mailmap
  36. CODE_OF_CONDUCT.md
  37. CONTRIBUTING.md
  38. LICENSE.TXT
  39. pyproject.toml
  40. README.md
  41. SECURITY.md
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